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From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
	alistair.francis@wdc.com, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback
Date: Fri,  3 Mar 2023 12:20:54 +0530	[thread overview]
Message-ID: <20230303065055.915652-2-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230303065055.915652-1-mchitale@ventanamicro.com>


Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 target/riscv/cpu.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0dd2f0c753..467d8467a3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1243,6 +1243,13 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 }
 
 #ifndef CONFIG_USER_ONLY
+static int64_t riscv_get_arch_id(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+
+    return cpu->env.mhartid;
+}
+
 #include "hw/core/sysemu-cpu-ops.h"
 
 static const struct SysemuCPUOps riscv_sysemu_ops = {
@@ -1297,6 +1304,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
     cc->sysemu_ops = &riscv_sysemu_ops;
+    cc->get_arch_id = riscv_get_arch_id;
 #endif
     cc->gdb_arch_name = riscv_gdb_arch_name;
     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
-- 
2.34.1



  reply	other threads:[~2023-03-03  6:51 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-03  6:50 [PATCH 0/2] Risc-V CPU state by hart ID Mayuresh Chitale
2023-03-03  6:50 ` Mayuresh Chitale [this message]
2023-03-03 20:05   ` [PATCH 1/2] target/riscv: cpu: Implement get_arch_id callback Daniel Henrique Barboza
2023-03-03  6:50 ` [PATCH 2/2] hw: intc: Use cpu_by_arch_id to fetch CPU state Mayuresh Chitale
2023-03-03 20:05   ` Daniel Henrique Barboza
2023-03-05 23:41 ` [PATCH 0/2] Risc-V CPU state by hart ID Palmer Dabbelt

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