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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() Date: Wed, 8 Mar 2023 17:19:24 -0300 Message-Id: <20230308201925.258223-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Mar 2023 20:20:22 -0000 We're getting ready to use riscv_cpu_validate_set_extensions() to unify the handling of write_misa() with the rest of the code base. But first we need to deal with RVG. The 'G' virtual extension enables a set of extensions in the CPU. At this moment, this is done at the start of our validation step in riscv_cpu_validate_set_extensions(). This means that enabling G will enable other extensions in the CPU before resuming the validation. This also means that, in case a write_misa() validation fails, we're going to set cpu->cfg attributes that are unrelated to misa_ext bits (icsr and ifencei). These would be 2 extra states that we would need to store to fallback from a validation failure. Since write_misa() is still on experimental state let's make our lives easier for now and disable RVG updates. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..02a5c2a5ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1347,6 +1347,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* Changing 'G' state is unsupported */ + if (val & RVG) { + return RISCV_EXCP_NONE; + } + /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ -- 2.39.2