From: Bartosz Golaszewski <brgl@bgdev.pl>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Subject: [PATCH v5 7/9] arm64: dts: qcom: sa8775p: add high-speed UART nodes
Date: Thu, 9 Mar 2023 11:37:50 +0100 [thread overview]
Message-ID: <20230309103752.173541-8-brgl@bgdev.pl> (raw)
In-Reply-To: <20230309103752.173541-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add two UART nodes that are known to be used by existing development
boards with this SoC.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 +++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index d1b2a6d30eae..468390edf049 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -490,6 +490,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
+
+ uart12: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x00a94000 0x0 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
};
qupv3_id_2: geniqup@8c0000 {
@@ -525,6 +540,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
status = "disabled";
};
+ uart17: serial@88c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x0088c000 0x0 0x4000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "qup-core", "qup-config";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
--
2.37.2
next prev parent reply other threads:[~2023-03-09 10:38 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-09 10:37 [PATCH v5 0/9] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 1/9] arm64: dts: qcom: sa8775p: add the QUPv3 #2 node Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 2/9] arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2 Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 3/9] arm64: dts: qcom: sa8775p: add the i2c18 node Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 4/9] arm64: dts: qcom: sa8775p-ride: enable i2c18 Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 5/9] arm64: dts: qcom: sa8775p: add the spi16 node Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 6/9] arm64: dts: qcom: sa8775p-ride: enable the SPI node Bartosz Golaszewski
2023-03-09 10:37 ` Bartosz Golaszewski [this message]
2023-03-09 10:37 ` [PATCH v5 8/9] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port Bartosz Golaszewski
2023-03-09 10:37 ` [PATCH v5 9/9] arm64: dts: qcom: sa8775p-ride: enable the BT " Bartosz Golaszewski
2023-03-16 14:48 ` [PATCH v5 0/9] arm64: dts: qcom: sa8775p-ride: enable relevant QUPv3 IPs Bartosz Golaszewski
2023-03-22 14:45 ` Bjorn Andersson
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