Re: [PATCH v5] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hi Hector,

hector.palacios@digi.com wrote on Fri, 10 Mar 2023 09:06:09 +0100:

> According to the ONFI specification, bit 0 of 'SDR timing mode support'
> (bytes 129-130) "shall be 1". That means the NAND supports at least
> timing mode 0.
> 
> NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
> which makes nand_choose_best_sdr_timings() return with error and the
> probe function to eventually fail.
> 
> Given that sdr_timing_modes bit 0 must be 1 by specification, force
> it in case the NAND reports it is not set. This is a safe assumption
> because the mode 0 is the minimum (safer) set of timings that the
> NAND can work with.
> 
> Signed-off-by: Hector Palacios <hector.palacios@digi.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

Actually you should not add my Signed-off-by like that. I will add it
when I take your patch.

In order to credit me (and that is very kind to you) you could have
instead used Suggested-by. If I had done more than just suggesting
something, another solution could have been to add a Co-developed-by
tag (and this time, my Signed-off-by would have been required).

Anyway, no need to resend, I'll fix it up when applying.

> Link: https://lore.kernel.org/linux-mtd/20230223165104.525852-1-hector.palacios@digi.com
> ---
> v5:
>   Simplify bitwise operation.
> v4:
>   Fix bitwise operation on __le16 type, per sparse warning.
> v3:
>   Forcibly set bit 0.
> v2:
>   Move patch to Hynix specific fixup hook.
>   Use BIT(0) macro.
> v1:
>   Implement generic patch in nand_base.c.
> 
>  drivers/mtd/nand/raw/nand_hynix.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
> index 0d4d4bbfdece..39076735a3fb 100644
> --- a/drivers/mtd/nand/raw/nand_hynix.c
> +++ b/drivers/mtd/nand/raw/nand_hynix.c
> @@ -728,8 +728,21 @@ static int hynix_nand_init(struct nand_chip *chip)
>  	return ret;
>  }
>  
> +static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
> +					struct nand_onfi_params *p)
> +{
> +	/*
> +	 * Certain chips might report a 0 on sdr_timing_mode field
> +	 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
> +	 * According to ONFI specification, bit 0 of this field "shall be 1".
> +	 * Forcibly set this bit.
> +	 */
> +	p->sdr_timing_modes |= cpu_to_le16(BIT(0));
> +}
> +
>  const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
>  	.detect = hynix_nand_decode_id,
>  	.init = hynix_nand_init,
>  	.cleanup = hynix_nand_cleanup,
> +	.fixup_onfi_param_page = hynix_fixup_onfi_param_page,
>  };


Thanks,
Miquèl

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