From: Ilya Leoshkevich <iii@linux.ibm.com>
To: Richard Henderson <richard.henderson@linaro.org>,
David Hildenbrand <david@redhat.com>
Cc: Thomas Huth <thuth@redhat.com>,
qemu-s390x@nongnu.org, qemu-devel@nongnu.org,
Ilya Leoshkevich <iii@linux.ibm.com>,
Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Subject: [PATCH v2 10/12] target/s390x: Handle STGRL to non-aligned addresses
Date: Mon, 13 Mar 2023 16:38:42 +0100 [thread overview]
Message-ID: <20230313153844.9231-11-iii@linux.ibm.com> (raw)
In-Reply-To: <20230313153844.9231-1-iii@linux.ibm.com>
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/tcg/insn-data.h.inc | 8 ++++----
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 30c02b3fcd6..597d968b0e8 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -842,14 +842,14 @@
/* STORE */
D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
- C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
- F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1)
- F(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1)
+ D(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0, 0)
+ E(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
+ E(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, 0, IF_AFP1)
E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
E(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
/* STORE RELATIVE LONG */
D(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN)
- C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
+ D(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0, MO_ALIGN)
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
C(0xe372, STCY, RXY_a, LD, r1_o, a2, 0, 0, st8, 0)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 29efbfab4e9..be95df73e9d 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4504,7 +4504,8 @@ static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),
+ MO_TEUQ | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
next prev parent reply other threads:[~2023-03-13 15:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-13 15:38 [PATCH v2 00/12] target/s390x: Handle unaligned accesses Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 01/12] target/s390x: Handle branching to odd addresses Ilya Leoshkevich
2023-03-13 19:54 ` Richard Henderson
2023-03-13 15:38 ` [PATCH v2 02/12] target/s390x: Handle EXECUTE of " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 03/12] target/s390x: Handle LGRL from non-aligned addresses Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 04/12] target/s390x: Handle LRL and LGFRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 05/12] target/s390x: Handle LLGFRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 06/12] target/s390x: Handle CRL and CGFRL with " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 07/12] target/s390x: Handle CGRL and CLGRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 08/12] target/s390x: Handle CLRL and CLGFRL " Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 09/12] target/s390x: Handle STRL to " Ilya Leoshkevich
2023-03-13 15:38 ` Ilya Leoshkevich [this message]
2023-03-13 15:38 ` [PATCH v2 11/12] target/s390x: Update do_unaligned_access() comment Ilya Leoshkevich
2023-03-13 15:38 ` [PATCH v2 12/12] tests/tcg/s390x: Test unaligned accesses Ilya Leoshkevich
2023-03-15 18:09 ` Thomas Huth
2023-03-15 18:13 ` Ilya Leoshkevich
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