From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76BF9C6FD1D for ; Fri, 17 Mar 2023 21:05:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229886AbjCQVFy (ORCPT ); Fri, 17 Mar 2023 17:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230156AbjCQVFx (ORCPT ); Fri, 17 Mar 2023 17:05:53 -0400 Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C955D31BE0; Fri, 17 Mar 2023 14:05:45 -0700 (PDT) Received: by mail-io1-f54.google.com with SMTP id b5so2901949iow.0; Fri, 17 Mar 2023 14:05:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679087145; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=5NecYJUuy8uaK/tVQe/yH+/ckF6yra+2Pis8jiBooqI=; b=EEkQpikadJ0do2Eio39rYWjS4wGEOJsBkyfNqhbrnXf13h433OUy4Ra+EjG4ROY5zn f8Sj7SFcDUUJukOFDcLd9ldhETd8W3Z9rBS9LmAsNrg5zRCFvqkVNY+il/Bv5TcDqwxR scU/SNz9A56QmjveB+cFDmzg3AyXIPhzECRReSS/5N+CfC89PcguczLSBUT7DWjWwH0Z PCxT7bt/aJKFGzqu3PId/QI3vma+/RIExQwWQ0Uovi4Mn1mELH2efiIqIhrPK59gJp6G a0ReyBwmvwfT2DMhFHXHEWz/G5FuGLQPQFAH+099Dx+KhbGhsz61637LprUjcvTyUFXB BtlQ== X-Gm-Message-State: AO0yUKWP6KKS1+aTz35hEuyPoP1AQY7STYyxOJ4WwFTZV27gXKw14q8j TQEP3NhHpT/VOna51n4Iqw== X-Google-Smtp-Source: AK7set8xIMQuQwJ6PDoZs6XtPl1fgkJczzCoyKvb4BiewQRvHyAeYv7nOvtmHPPFiuOhaMQjb5HJ4w== X-Received: by 2002:a6b:e216:0:b0:753:121f:72a7 with SMTP id z22-20020a6be216000000b00753121f72a7mr23373ioc.8.1679087145050; Fri, 17 Mar 2023 14:05:45 -0700 (PDT) Received: from robh_at_kernel.org ([64.188.179.249]) by smtp.gmail.com with ESMTPSA id cs6-20020a056638470600b003e9e5e1aacasm1005332jab.143.2023.03.17.14.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:05:44 -0700 (PDT) Received: (nullmailer pid 2804141 invoked by uid 1000); Fri, 17 Mar 2023 21:05:42 -0000 Date: Fri, 17 Mar 2023 16:05:42 -0500 From: Rob Herring To: Chia-Wei Wang Cc: vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org, joel@jms.id.au, andrew@aj.id.au, gregkh@linuxfoundation.org, jirislaby@kernel.org, pmenzel@molgen.mpg.de, ilpo.jarvinen@linux.intel.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, openbmc@lists.ozlabs.org Subject: Re: [PATCH v2 2/5] dt-bindings: dmaengine: Add AST2600 UDMA bindings Message-ID: <20230317210542.GB2790192-robh@kernel.org> References: <20230314021817.30446-1-chiawei_wang@aspeedtech.com> <20230314021817.30446-3-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230314021817.30446-3-chiawei_wang@aspeedtech.com> Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Tue, Mar 14, 2023 at 10:18:14AM +0800, Chia-Wei Wang wrote: > Add the dmaengine bindings for the UART DMA engine of Aspeed AST2600 SoC. > > Signed-off-by: Chia-Wei Wang > --- > .../bindings/dma/aspeed,ast2600-udma.yaml | 56 +++++++++++++++++++ > include/dt-bindings/dma/ast2600-udma.h | 40 +++++++++++++ > 2 files changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > create mode 100644 include/dt-bindings/dma/ast2600-udma.h > > diff --git a/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > new file mode 100644 > index 000000000000..f92e06ac9f39 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/aspeed,ast2600-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed AST2600 UART DMA controller > + > +maintainers: > + - Chia-Wei Wang > + > +description: | Don't need '|' > + The Aspeed AST2600 UDMA controller provides direct memory access capabilities > + for the NS16550A-compatible UART devices inside AST2600 SoCs. UDMA supports 28 > + DMA channels and each UART device has its dedicated pair of TX and RX channels. > + > +allOf: > + - $ref: "dma-controller.yaml#" Drop quotes > + > +properties: > + compatible: > + const: aspeed,ast2600-udma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#dma-cells": > + const: 1 > + > + dma-channels: > + maximum: 28 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#dma-cells" > + - dma-channels > + > +additionalProperties: false > + > +examples: > + - | > + #include > + udma: dma-controller@1e79e000 { Drop unused label. > + compatible = "aspeed,ast2600-udma"; > + reg = <0x1e79e000 0x1000>; > + interrupts = ; > + dma-channels = <28>; > + #dma-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/dma/ast2600-udma.h b/include/dt-bindings/dma/ast2600-udma.h > new file mode 100644 > index 000000000000..0b92035b94f1 > --- /dev/null > +++ b/include/dt-bindings/dma/ast2600-udma.h > @@ -0,0 +1,40 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Headers should be dual licensed. However, similar to interrupts, we don't normally do defines for DMA request numbers. It's only when we make up the numbering (e.g. clock ids). Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Date: Fri, 17 Mar 2023 16:05:42 -0500 Subject: [PATCH v2 2/5] dt-bindings: dmaengine: Add AST2600 UDMA bindings In-Reply-To: <20230314021817.30446-3-chiawei_wang@aspeedtech.com> References: <20230314021817.30446-1-chiawei_wang@aspeedtech.com> <20230314021817.30446-3-chiawei_wang@aspeedtech.com> Message-ID: <20230317210542.GB2790192-robh@kernel.org> List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Tue, Mar 14, 2023 at 10:18:14AM +0800, Chia-Wei Wang wrote: > Add the dmaengine bindings for the UART DMA engine of Aspeed AST2600 SoC. > > Signed-off-by: Chia-Wei Wang > --- > .../bindings/dma/aspeed,ast2600-udma.yaml | 56 +++++++++++++++++++ > include/dt-bindings/dma/ast2600-udma.h | 40 +++++++++++++ > 2 files changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > create mode 100644 include/dt-bindings/dma/ast2600-udma.h > > diff --git a/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > new file mode 100644 > index 000000000000..f92e06ac9f39 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/aspeed,ast2600-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed AST2600 UART DMA controller > + > +maintainers: > + - Chia-Wei Wang > + > +description: | Don't need '|' > + The Aspeed AST2600 UDMA controller provides direct memory access capabilities > + for the NS16550A-compatible UART devices inside AST2600 SoCs. UDMA supports 28 > + DMA channels and each UART device has its dedicated pair of TX and RX channels. > + > +allOf: > + - $ref: "dma-controller.yaml#" Drop quotes > + > +properties: > + compatible: > + const: aspeed,ast2600-udma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#dma-cells": > + const: 1 > + > + dma-channels: > + maximum: 28 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#dma-cells" > + - dma-channels > + > +additionalProperties: false > + > +examples: > + - | > + #include > + udma: dma-controller at 1e79e000 { Drop unused label. > + compatible = "aspeed,ast2600-udma"; > + reg = <0x1e79e000 0x1000>; > + interrupts = ; > + dma-channels = <28>; > + #dma-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/dma/ast2600-udma.h b/include/dt-bindings/dma/ast2600-udma.h > new file mode 100644 > index 000000000000..0b92035b94f1 > --- /dev/null > +++ b/include/dt-bindings/dma/ast2600-udma.h > @@ -0,0 +1,40 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Headers should be dual licensed. However, similar to interrupts, we don't normally do defines for DMA request numbers. It's only when we make up the numbering (e.g. clock ids). Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7DFDDC6FD1D for ; Fri, 17 Mar 2023 21:06:26 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PdcB85x1kz3f4t for ; Sat, 18 Mar 2023 08:06:24 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=209.85.166.49; helo=mail-io1-f49.google.com; envelope-from=robherring2@gmail.com; receiver=) Received: from mail-io1-f49.google.com (mail-io1-f49.google.com [209.85.166.49]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4Pdc9S13Mqz3bWj; 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Fri, 17 Mar 2023 14:05:45 -0700 (PDT) Received: from robh_at_kernel.org ([64.188.179.249]) by smtp.gmail.com with ESMTPSA id cs6-20020a056638470600b003e9e5e1aacasm1005332jab.143.2023.03.17.14.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:05:44 -0700 (PDT) Received: (nullmailer pid 2804141 invoked by uid 1000); Fri, 17 Mar 2023 21:05:42 -0000 Date: Fri, 17 Mar 2023 16:05:42 -0500 From: Rob Herring To: Chia-Wei Wang Subject: Re: [PATCH v2 2/5] dt-bindings: dmaengine: Add AST2600 UDMA bindings Message-ID: <20230317210542.GB2790192-robh@kernel.org> References: <20230314021817.30446-1-chiawei_wang@aspeedtech.com> <20230314021817.30446-3-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230314021817.30446-3-chiawei_wang@aspeedtech.com> X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pmenzel@molgen.mpg.de, linux-serial@vger.kernel.org, linux-aspeed@lists.ozlabs.org, devicetree@vger.kernel.org, andrew@aj.id.au, gregkh@linuxfoundation.org, openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org, vkoul@kernel.org, joel@jms.id.au, krzysztof.kozlowski+dt@linaro.org, dmaengine@vger.kernel.org, ilpo.jarvinen@linux.intel.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" On Tue, Mar 14, 2023 at 10:18:14AM +0800, Chia-Wei Wang wrote: > Add the dmaengine bindings for the UART DMA engine of Aspeed AST2600 SoC. > > Signed-off-by: Chia-Wei Wang > --- > .../bindings/dma/aspeed,ast2600-udma.yaml | 56 +++++++++++++++++++ > include/dt-bindings/dma/ast2600-udma.h | 40 +++++++++++++ > 2 files changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > create mode 100644 include/dt-bindings/dma/ast2600-udma.h > > diff --git a/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > new file mode 100644 > index 000000000000..f92e06ac9f39 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/aspeed,ast2600-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed AST2600 UART DMA controller > + > +maintainers: > + - Chia-Wei Wang > + > +description: | Don't need '|' > + The Aspeed AST2600 UDMA controller provides direct memory access capabilities > + for the NS16550A-compatible UART devices inside AST2600 SoCs. UDMA supports 28 > + DMA channels and each UART device has its dedicated pair of TX and RX channels. > + > +allOf: > + - $ref: "dma-controller.yaml#" Drop quotes > + > +properties: > + compatible: > + const: aspeed,ast2600-udma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#dma-cells": > + const: 1 > + > + dma-channels: > + maximum: 28 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#dma-cells" > + - dma-channels > + > +additionalProperties: false > + > +examples: > + - | > + #include > + udma: dma-controller@1e79e000 { Drop unused label. > + compatible = "aspeed,ast2600-udma"; > + reg = <0x1e79e000 0x1000>; > + interrupts = ; > + dma-channels = <28>; > + #dma-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/dma/ast2600-udma.h b/include/dt-bindings/dma/ast2600-udma.h > new file mode 100644 > index 000000000000..0b92035b94f1 > --- /dev/null > +++ b/include/dt-bindings/dma/ast2600-udma.h > @@ -0,0 +1,40 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Headers should be dual licensed. However, similar to interrupts, we don't normally do defines for DMA request numbers. It's only when we make up the numbering (e.g. clock ids). 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Fri, 17 Mar 2023 14:05:45 -0700 (PDT) Received: from robh_at_kernel.org ([64.188.179.249]) by smtp.gmail.com with ESMTPSA id cs6-20020a056638470600b003e9e5e1aacasm1005332jab.143.2023.03.17.14.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Mar 2023 14:05:44 -0700 (PDT) Received: (nullmailer pid 2804141 invoked by uid 1000); Fri, 17 Mar 2023 21:05:42 -0000 Date: Fri, 17 Mar 2023 16:05:42 -0500 From: Rob Herring To: Chia-Wei Wang Cc: vkoul@kernel.org, krzysztof.kozlowski+dt@linaro.org, joel@jms.id.au, andrew@aj.id.au, gregkh@linuxfoundation.org, jirislaby@kernel.org, pmenzel@molgen.mpg.de, ilpo.jarvinen@linux.intel.com, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, openbmc@lists.ozlabs.org Subject: Re: [PATCH v2 2/5] dt-bindings: dmaengine: Add AST2600 UDMA bindings Message-ID: <20230317210542.GB2790192-robh@kernel.org> References: <20230314021817.30446-1-chiawei_wang@aspeedtech.com> <20230314021817.30446-3-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230314021817.30446-3-chiawei_wang@aspeedtech.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230317_140546_725703_8F878AA9 X-CRM114-Status: GOOD ( 15.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 14, 2023 at 10:18:14AM +0800, Chia-Wei Wang wrote: > Add the dmaengine bindings for the UART DMA engine of Aspeed AST2600 SoC. > > Signed-off-by: Chia-Wei Wang > --- > .../bindings/dma/aspeed,ast2600-udma.yaml | 56 +++++++++++++++++++ > include/dt-bindings/dma/ast2600-udma.h | 40 +++++++++++++ > 2 files changed, 96 insertions(+) > create mode 100644 Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > create mode 100644 include/dt-bindings/dma/ast2600-udma.h > > diff --git a/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > new file mode 100644 > index 000000000000..f92e06ac9f39 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/aspeed,ast2600-udma.yaml > @@ -0,0 +1,56 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/aspeed,ast2600-udma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Aspeed AST2600 UART DMA controller > + > +maintainers: > + - Chia-Wei Wang > + > +description: | Don't need '|' > + The Aspeed AST2600 UDMA controller provides direct memory access capabilities > + for the NS16550A-compatible UART devices inside AST2600 SoCs. UDMA supports 28 > + DMA channels and each UART device has its dedicated pair of TX and RX channels. > + > +allOf: > + - $ref: "dma-controller.yaml#" Drop quotes > + > +properties: > + compatible: > + const: aspeed,ast2600-udma > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + "#dma-cells": > + const: 1 > + > + dma-channels: > + maximum: 28 > + > +required: > + - compatible > + - reg > + - interrupts > + - "#dma-cells" > + - dma-channels > + > +additionalProperties: false > + > +examples: > + - | > + #include > + udma: dma-controller@1e79e000 { Drop unused label. > + compatible = "aspeed,ast2600-udma"; > + reg = <0x1e79e000 0x1000>; > + interrupts = ; > + dma-channels = <28>; > + #dma-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/dma/ast2600-udma.h b/include/dt-bindings/dma/ast2600-udma.h > new file mode 100644 > index 000000000000..0b92035b94f1 > --- /dev/null > +++ b/include/dt-bindings/dma/ast2600-udma.h > @@ -0,0 +1,40 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Headers should be dual licensed. However, similar to interrupts, we don't normally do defines for DMA request numbers. It's only when we make up the numbering (e.g. clock ids). Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel