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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id ax35-20020a05687c022300b0017243edbe5bsm5586817oac.58.2023.03.22.15.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 15:20:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation Date: Wed, 22 Mar 2023 19:19:39 -0300 Message-Id: <20230322222004.357013-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=dbarboza@ventanamicro.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Mar 2023 22:29:52 -0000 Hi, In this version I simplified the logic used in write_misa() after reviews from Weiwei Li. The patch that handled RVV activation was removed, making RVV a regular MISA bit to activate/deactivate. We're also checking whether one of the IMAFD extensions got disabled during write_misa() and, if that's the case, we'll clear RVG. Series is based on top of Alistair's riscv-to-apply.next. Patches acked: 1-5. Changes from v3: - patch 11: - remove c/u/s cpu->cfg assignment from rv64_thead_c906_cpu_init() - patch 14: - add RVG in set_misa() call inside rv64_thead_c906_cpu_init() - remove cpu->cfg.ext_g assignment from rv64_thead_c906_cpu_init() - patch 15: - remove ext_zfinx verification from riscv_cpu_enable_g() - patch 25: - do not call riscv_cpu_enable_g() in write_misa() - enable/disable RVG extensions manually in write_misa() - patch 26: removed - v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg05097.html Daniel Henrique Barboza (25): target/riscv/cpu.c: add riscv_cpu_validate_v() target/riscv/cpu.c: remove set_vext_version() target/riscv/cpu.c: remove set_priv_version() target/riscv: add PRIV_VERSION_LATEST target/riscv/cpu.c: add priv_spec validate/disable_exts helpers target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() target/riscv: move pmp and epmp validations to validate_set_extensions() target/riscv/cpu.c: validate extensions before riscv_timer_init() target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() target/riscv/cpu.c: set cpu config in set_misa() target/riscv/cpu.c: redesign register_cpu_props() target/riscv: put env->misa_ext <-> cpu->cfg code into helpers target/riscv: add RVG target/riscv/cpu.c: split RVG code from validate_set_extensions() target/riscv/cpu.c: add riscv_cpu_validate_misa_ext() target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() target/riscv: error out on priv failure for RVH target/riscv: write env->misa_ext* in register_generic_cpu_props() target/riscv: make validate_misa_ext() use a misa_ext val target/riscv: split riscv_cpu_validate_set_extensions() target/riscv: use misa_ext val in riscv_cpu_validate_extensions() target/riscv: rework write_misa() target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() target/riscv: handle RVG updates in write_misa() target/riscv/cpu.c | 654 ++++++++++++++++++++++++++++----------------- target/riscv/cpu.h | 14 +- target/riscv/csr.c | 72 +++-- 3 files changed, 463 insertions(+), 277 deletions(-) -- 2.39.2