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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id ax35-20020a05687c022300b0017243edbe5bsm5586817oac.58.2023.03.22.15.21.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Mar 2023 15:21:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v4 25/25] target/riscv: handle RVG updates in write_misa() Date: Wed, 22 Mar 2023 19:20:04 -0300 Message-Id: <20230322222004.357013-26-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230322222004.357013-1-dbarboza@ventanamicro.com> References: <20230322222004.357013-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Mar 2023 22:23:02 -0000 RVG is enabled when IMAFD_Zicsr_Zifencei is also enabled. Change write_misa() to enable IMAFD if G is being written in the CSR. Likewise, RVG should be disabled if any of IMAFD got disabled during the process. Clear RVG in this case. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 839862f1a8..1c0f438dfb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1381,6 +1381,14 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= RVE; } + if (val & RVG && !(env->misa_ext & RVG)) { + /* + * If the write wants to enable RVG, enable all its + * dependencies as well. + */ + val |= RVI | RVM | RVA | RVF | RVD; + } + /* * This flow is similar to what riscv_cpu_realize() does, * with the difference that we will update env->misa_ext @@ -1396,6 +1404,12 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + if (!(val & RVI && val & RVM && val & RVA && + val & RVF && val & RVD)) { + /* Disable RVG if any of its dependencies were disabled */ + val &= ~RVG; + } + riscv_cpu_commit_cpu_cfg(cpu, val); if (!(val & RVF)) { -- 2.39.2