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([177.95.89.231]) by smtp.gmail.com with ESMTPSA id s9-20020a4a9689000000b005255e556399sm11985361ooi.43.2023.03.27.15.49.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 15:49:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 00/19] remove MISA ext_N flags from cpu->cfg Date: Mon, 27 Mar 2023 19:49:15 -0300 Message-Id: <20230327224934.363314-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Mar 2023 22:49:49 -0000 Hi, In this version we have changes in patch 3 suggested by Richard Henderson in the v1 review. Patches are based on Alistair's riscv-to-apply.next. Changes from v1: - patch 3: - change misa_ext_cfgs[] to a const array - remove dynamic allocation of strings and use the string literals - v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06337.html Daniel Henrique Barboza (19): target/riscv: sync env->misa_ext* with cpu->cfg in realize() target/riscv: remove MISA properties from isa_edata_arr[] target/riscv: introduce riscv_cpu_add_misa_properties() target/riscv: remove cpu->cfg.ext_a target/riscv: remove cpu->cfg.ext_c target/riscv: remove cpu->cfg.ext_d target/riscv: remove cpu->cfg.ext_f target/riscv: remove cpu->cfg.ext_i target/riscv: remove cpu->cfg.ext_e target/riscv: remove cpu->cfg.ext_m target/riscv: remove cpu->cfg.ext_s target/riscv: remove cpu->cfg.ext_u target/riscv: remove cpu->cfg.ext_h target/riscv: remove cpu->cfg.ext_j target/riscv: remove cpu->cfg.ext_v target/riscv: remove riscv_cpu_sync_misa_cfg() target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() target/riscv: add RVG and remove cpu->cfg.ext_g target/riscv/cpu.c: redesign register_cpu_props() target/riscv/cpu.c | 268 ++++++++++++++++++++++++--------------------- target/riscv/cpu.h | 19 +--- 2 files changed, 144 insertions(+), 143 deletions(-) -- 2.39.2