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diff for duplicates of <20230403093310.2271142-2-apatel@ventanamicro.com>

diff --git a/a/1.txt b/N1/1.txt
index 302748c..0064379 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -171,3 +171,9 @@ index 0e571f6483d9..3c8d68152bce 100644
  # define SR_PP		SR_SPP
 -- 
 2.34.1
+
+
+_______________________________________________
+linux-riscv mailing list
+linux-riscv@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-riscv
diff --git a/a/content_digest b/N1/content_digest
index 744076c..a394b54 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,20 @@
  "From\0Anup Patel <apatel@ventanamicro.com>\0"
  "Subject\0[PATCH v3 1/8] RISC-V: Add AIA related CSR defines\0"
  "Date\0Mon,  3 Apr 2023 15:03:03 +0530\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0Paolo Bonzini <pbonzini@redhat.com>"
+ " Atish Patra <atishp@atishpatra.org>\0"
+ "Cc\0Palmer Dabbelt <palmer@dabbelt.com>"
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Andrew Jones <ajones@ventanamicro.com>
+  Anup Patel <anup@brainfault.org>
+  kvm@vger.kernel.org
+  kvm-riscv@lists.infradead.org
+  linux-riscv@lists.infradead.org
+  linux-kernel@vger.kernel.org
+  Anup Patel <apatel@ventanamicro.com>
+  Conor Dooley <conor.dooley@microchip.com>
+  Atish Patra <atishp@rivosinc.com>
+ " Palmer Dabbelt <palmer@rivosinc.com>\0"
  "\00:1\0"
  "b\0"
  "The RISC-V AIA specification improves handling per-HART local interrupts\n"
@@ -177,6 +190,12 @@
  " # define SR_PIE\t\tSR_SPIE\n"
  " # define SR_PP\t\tSR_SPP\n"
  "-- \n"
- 2.34.1
+ "2.34.1\n"
+ "\n"
+ "\n"
+ "_______________________________________________\n"
+ "linux-riscv mailing list\n"
+ "linux-riscv@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-riscv
 
-36ac1ca6eb2733776425f9f2a7f0e86ede95bcf960e5177619dd86d1592a0042
+2c1d13891a368f957d6f19895d78c6b8dba388e083cdd2627e1cd93545dc7972

diff --git a/a/content_digest b/N2/content_digest
index 744076c..ec60da8 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,7 +2,20 @@
  "From\0Anup Patel <apatel@ventanamicro.com>\0"
  "Subject\0[PATCH v3 1/8] RISC-V: Add AIA related CSR defines\0"
  "Date\0Mon,  3 Apr 2023 15:03:03 +0530\0"
- "To\0kvm-riscv@lists.infradead.org\0"
+ "To\0Paolo Bonzini <pbonzini@redhat.com>"
+ " Atish Patra <atishp@atishpatra.org>\0"
+ "Cc\0Palmer Dabbelt <palmer@dabbelt.com>"
+  Paul Walmsley <paul.walmsley@sifive.com>
+  Andrew Jones <ajones@ventanamicro.com>
+  Anup Patel <anup@brainfault.org>
+  kvm@vger.kernel.org
+  kvm-riscv@lists.infradead.org
+  linux-riscv@lists.infradead.org
+  linux-kernel@vger.kernel.org
+  Anup Patel <apatel@ventanamicro.com>
+  Conor Dooley <conor.dooley@microchip.com>
+  Atish Patra <atishp@rivosinc.com>
+ " Palmer Dabbelt <palmer@rivosinc.com>\0"
  "\00:1\0"
  "b\0"
  "The RISC-V AIA specification improves handling per-HART local interrupts\n"
@@ -179,4 +192,4 @@
  "-- \n"
  2.34.1
 
-36ac1ca6eb2733776425f9f2a7f0e86ede95bcf960e5177619dd86d1592a0042
+2cd848ff6b4b8836790ba01be9c43af813caeccb26301220f6c62c9bb1b30d8d

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