From: Rushil Gupta <rushilg@google.com>
To: qi.z.zhang@intel.com, ferruh.yigit@amd.com
Cc: bruce.richardson@intel.com, dev@dpdk.org,
Rushil Gupta <rushilg@google.com>,
Junfeng Guo <junfeng.guo@intel.com>
Subject: [PATCH 1/1] net/gve: update base code for DQO
Date: Mon, 10 Apr 2023 21:59:08 -0700 [thread overview]
Message-ID: <20230411045908.844901-2-rushilg@google.com> (raw)
In-Reply-To: <20230411045908.844901-1-rushilg@google.com>
Update gve base code to support DQO.
This patch is based on this:
https://patchwork.dpdk.org/project/dpdk/list/?series=27647&state=*
Signed-off-by: Rushil Gupta <rushilg@google.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
drivers/net/gve/base/gve.h | 1 +
drivers/net/gve/base/gve_adminq.c | 10 +++++-----
drivers/net/gve/base/gve_desc_dqo.h | 4 ----
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/net/gve/base/gve.h b/drivers/net/gve/base/gve.h
index 2dc4507acb..2b7cf7d99b 100644
--- a/drivers/net/gve/base/gve.h
+++ b/drivers/net/gve/base/gve.h
@@ -7,6 +7,7 @@
#define _GVE_H_
#include "gve_desc.h"
+#include "gve_desc_dqo.h"
#define GVE_VERSION "1.3.0"
#define GVE_VERSION_PREFIX "GVE-"
diff --git a/drivers/net/gve/base/gve_adminq.c b/drivers/net/gve/base/gve_adminq.c
index e745b709b2..e963f910a0 100644
--- a/drivers/net/gve/base/gve_adminq.c
+++ b/drivers/net/gve/base/gve_adminq.c
@@ -497,11 +497,11 @@ static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index)
cmd.create_tx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
} else {
cmd.create_tx_queue.tx_ring_size =
- cpu_to_be16(txq->nb_tx_desc);
+ cpu_to_be16(priv->tx_desc_cnt);
cmd.create_tx_queue.tx_comp_ring_addr =
- cpu_to_be64(txq->complq->tx_ring_phys_addr);
+ cpu_to_be64(txq->compl_ring_phys_addr);
cmd.create_tx_queue.tx_comp_ring_size =
- cpu_to_be16(priv->tx_compq_size);
+ cpu_to_be16(priv->tx_compq_size * DQO_TX_MULTIPLIER);
}
return gve_adminq_issue_cmd(priv, &cmd);
@@ -549,9 +549,9 @@ static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
cmd.create_rx_queue.rx_ring_size =
cpu_to_be16(priv->rx_desc_cnt);
cmd.create_rx_queue.rx_desc_ring_addr =
- cpu_to_be64(rxq->rx_ring_phys_addr);
+ cpu_to_be64(rxq->compl_ring_phys_addr);
cmd.create_rx_queue.rx_data_ring_addr =
- cpu_to_be64(rxq->bufq->rx_ring_phys_addr);
+ cpu_to_be64(rxq->rx_ring_phys_addr);
cmd.create_rx_queue.packet_buffer_size =
cpu_to_be16(rxq->rx_buf_len);
cmd.create_rx_queue.rx_buff_ring_size =
diff --git a/drivers/net/gve/base/gve_desc_dqo.h b/drivers/net/gve/base/gve_desc_dqo.h
index ee1afdecb8..bb4a18d4d1 100644
--- a/drivers/net/gve/base/gve_desc_dqo.h
+++ b/drivers/net/gve/base/gve_desc_dqo.h
@@ -13,10 +13,6 @@
#define GVE_TX_MAX_HDR_SIZE_DQO 255
#define GVE_TX_MIN_TSO_MSS_DQO 88
-#ifndef __LITTLE_ENDIAN_BITFIELD
-#error "Only little endian supported"
-#endif
-
/* Basic TX descriptor (DTYPE 0x0C) */
struct gve_tx_pkt_desc_dqo {
__le64 buf_addr;
--
2.40.0.577.gac1e443424-goog
next prev parent reply other threads:[~2023-04-11 4:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 4:59 [PATCH 0/1] *** Update drivers/net/gve/base code for DQO *** Rushil Gupta
2023-04-11 4:59 ` Rushil Gupta [this message]
2023-04-11 6:51 ` [PATCH 1/1] net/gve: update base code for DQO Guo, Junfeng
2023-04-12 8:50 ` Ferruh Yigit
2023-04-12 9:09 ` Guo, Junfeng
2023-04-12 9:34 ` Ferruh Yigit
2023-04-12 9:41 ` Guo, Junfeng
2023-04-12 15:42 ` Rushil Gupta
2023-04-12 16:02 ` Ferruh Yigit
2023-04-12 18:04 ` Rushil Gupta
2023-04-14 5:17 ` Rushil Gupta
2023-04-14 11:00 ` Ferruh Yigit
2023-05-04 8:30 ` Ferruh Yigit
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