From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8765C77B6F for ; Tue, 11 Apr 2023 13:09:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229787AbjDKNJ6 (ORCPT ); Tue, 11 Apr 2023 09:09:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjDKNJv (ORCPT ); Tue, 11 Apr 2023 09:09:51 -0400 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1E014690; Tue, 11 Apr 2023 06:09:47 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8667320007; Tue, 11 Apr 2023 13:09:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1681218585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zj1JtAKrv3GVkrzExsf9B7vpxAMSpGNgfjgQje0eTak=; b=oNG2Rb7etLGd3op/Iz2fmq0xokA2awaHaTUwmpMIqfWRcdiVNffJhH1OiD/NJa8U8VhbyA yF9MXtYH8Fxz3M+cAq/7V/oq1xoDx4mXB50I/MCViACuf5Xj/3sm+jiFSUhQyd/GFiKSU+ MvbhXoQ5xcQFvUgIZ6glZLEM1HPSvT3ZkSE8cIw3GiRKuf3ey7u+ch+9vo/URZlNg8hBkX sdQ/9ZojYLUArwz1K4ERP3d5/cBFRF6/83yyqSdXppNVR0gRdgwuMipAeMDZ8IGKN7s335 n6r/K2t/A0PaaBtBH3FUkAWJV3CrDikEbkeZlUHa/BD6XrUBmGFFsgVYyetBaQ== Date: Tue, 11 Apr 2023 15:09:30 +0200 From: Miquel Raynal To: Geert Uytterhoeven Cc: Maxime Ripard , Michael Turquette , Stephen Boyd , Andreas =?UTF-8?B?RsOkcmJlcg==?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Dinh Nguyen , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, Gareth Williams , Herve Codina , Ralph Siemsen Subject: Re: [PATCH v3 28/65] clk: renesas: r9a06g032: Add a determine_rate hook Message-ID: <20230411150930.4fb22d7e@xps-13> In-Reply-To: References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-28-9a1358472d52@cerno.tech> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hi Geert & Maxime, geert@linux-m68k.org wrote on Tue, 11 Apr 2023 12:27:38 +0200: > CC Gareth, Herv=C3=A9, Miquel, Ralph >=20 > On Tue, Apr 4, 2023 at 2:44=E2=80=AFPM Maxime Ripard = wrote: > > The Renesas r9a06g032 bitselect clock implements a mux with a set_parent > > hook, but doesn't provide a determine_rate implementation. > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > change the parent of a clock. However, the most likely candidate to > > trigger that parent change is a call to clk_set_rate(), with > > determine_rate() figuring out which parent is the best suited for a > > given rate. > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > used, and it doesn't look like there's any obvious user for that clock. > > > > So, the set_parent hook is effectively unused, possibly because of an > > oversight. However, it could also be an explicit decision by the > > original author to avoid any reparenting but through an explicit call to > > clk_set_parent(). > > > > The latter case would be equivalent to setting the flag > > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook > > to __clk_mux_determine_rate(). Indeed, if no determine_rate > > implementation is provided, clk_round_rate() (through > > clk_core_round_rate_nolock()) will call itself on the parent if > > CLK_SET_RATE_PARENT is set, and will not change the clock rate > > otherwise. __clk_mux_determine_rate() has the exact same behavior when > > CLK_SET_RATE_NO_REPARENT is set. > > > > And if it was an oversight, then we are at least explicit about our > > behavior now and it can be further refined down the line. > > > > Signed-off-by: Maxime Ripard =20 >=20 > LGTM, so > Reviewed-by: Geert Uytterhoeven I searched for 'possible callers', I didn't find any places where this would be used on the consumer side. However, downstream, there is a rzn1-clock-bitselect.c clock driver which states: + * This clock provider handles the case of the RZN1 where you have periphe= rals + * that have two potential clock source and two gates, one for each of the + * clock source - the used clock source (for all sub clocks) is selected b= y a + * single bit. + * That single bit affects all sub-clocks, and therefore needs to change t= he + * active gate (and turn the others off) and force a recalculation of the = rates. I don't know how much of this file has been upstreamed (under a different form) but this might very well be related to the fact that reparenting in some cases would be a major issue and thus needs to be avoided unless done on purpose (guessing?). Maybe Ralph can comment, but for what I understand, Reviewed-by: Miquel Raynal > But I do not have the hardware. >=20 > > --- a/drivers/clk/renesas/r9a06g032-clocks.c > > +++ b/drivers/clk/renesas/r9a06g032-clocks.c > > @@ -1121,6 +1121,7 @@ static int r9a06g032_clk_mux_set_parent(struct cl= k_hw *hw, u8 index) > > } > > > > static const struct clk_ops clk_bitselect_ops =3D { > > + .determine_rate =3D __clk_mux_determine_rate, > > .get_parent =3D r9a06g032_clk_mux_get_parent, > > .set_parent =3D r9a06g032_clk_mux_set_parent, > > }; > > @@ -1145,7 +1146,7 @@ r9a06g032_register_bitsel(struct r9a06g032_priv *= clocks, > > > > init.name =3D desc->name; > > init.ops =3D &clk_bitselect_ops; > > - init.flags =3D CLK_SET_RATE_PARENT; > > + init.flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; > > init.parent_names =3D names; > > init.num_parents =3D 2; > > =20 >=20 > Gr{oetje,eeting}s, >=20 > Geert >=20 Thanks, Miqu=C3=A8l From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B9B5C76196 for ; Tue, 11 Apr 2023 13:09:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YfPHRfPIcn2ktzjKqTkRYIgOFO5lGzh7/SkMOvTFWvk=; b=McsYlblOe5zkjb GQZn3jrlya0gYbcXD1+XAbnlV/H8vbnmpONV+zXiytuaBjP/X870+ksAmDVSJiAA5LLkLWN7adk+8 KpdXJ47LarekbyyCEwsgNy2U5tQ/jKl4mc0o7ZlaL7h9s+w2yCCTGUvVUbybd0LO6YN6jLEGG+DO+ sPsn5YYVWhasQsAVlPXxwZf0VIva7oB1IyC6R6JdF993nbYIkDqTzdorTmzojkJMegWrDU0jXeAvD maRxYpFq8MyDkVhrKTdReEgbIucLMUG5EKHgtvGK+jPHjx5VjKjUA8vtZL7mqk2SKgOY0TTRDr4Vl osIaEhjIgfLWU6s3wVew==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pmDky-0004Zy-02; Tue, 11 Apr 2023 13:09:56 +0000 Received: from relay7-d.mail.gandi.net ([217.70.183.200]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pmDks-0004YW-2A; Tue, 11 Apr 2023 13:09:52 +0000 Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8667320007; Tue, 11 Apr 2023 13:09:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1681218585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zj1JtAKrv3GVkrzExsf9B7vpxAMSpGNgfjgQje0eTak=; b=oNG2Rb7etLGd3op/Iz2fmq0xokA2awaHaTUwmpMIqfWRcdiVNffJhH1OiD/NJa8U8VhbyA yF9MXtYH8Fxz3M+cAq/7V/oq1xoDx4mXB50I/MCViACuf5Xj/3sm+jiFSUhQyd/GFiKSU+ MvbhXoQ5xcQFvUgIZ6glZLEM1HPSvT3ZkSE8cIw3GiRKuf3ey7u+ch+9vo/URZlNg8hBkX sdQ/9ZojYLUArwz1K4ERP3d5/cBFRF6/83yyqSdXppNVR0gRdgwuMipAeMDZ8IGKN7s335 n6r/K2t/A0PaaBtBH3FUkAWJV3CrDikEbkeZlUHa/BD6XrUBmGFFsgVYyetBaQ== Date: Tue, 11 Apr 2023 15:09:30 +0200 From: Miquel Raynal To: Geert Uytterhoeven Cc: Maxime Ripard , Michael Turquette , Stephen Boyd , Andreas =?UTF-8?B?RsOkcmJlcg==?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Dinh Nguyen , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, Gareth Williams , Herve Codina , Ralph Siemsen Subject: Re: [PATCH v3 28/65] clk: renesas: r9a06g032: Add a determine_rate hook Message-ID: <20230411150930.4fb22d7e@xps-13> In-Reply-To: References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-28-9a1358472d52@cerno.tech> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230411_060950_969008_5FC5154A X-CRM114-Status: GOOD ( 36.24 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org SGkgR2VlcnQgJiBNYXhpbWUsCgpnZWVydEBsaW51eC1tNjhrLm9yZyB3cm90ZSBvbiBUdWUsIDEx IEFwciAyMDIzIDEyOjI3OjM4ICswMjAwOgoKPiBDQyBHYXJldGgsIEhlcnbDqSwgTWlxdWVsLCBS YWxwaAo+IAo+IE9uIFR1ZSwgQXByIDQsIDIwMjMgYXQgMjo0NOKAr1BNIE1heGltZSBSaXBhcmQg PG1heGltZUBjZXJuby50ZWNoPiB3cm90ZToKPiA+IFRoZSBSZW5lc2FzIHI5YTA2ZzAzMiBiaXRz ZWxlY3QgY2xvY2sgaW1wbGVtZW50cyBhIG11eCB3aXRoIGEgc2V0X3BhcmVudAo+ID4gaG9vaywg YnV0IGRvZXNuJ3QgcHJvdmlkZSBhIGRldGVybWluZV9yYXRlIGltcGxlbWVudGF0aW9uLgo+ID4K PiA+IFRoaXMgaXMgYSBiaXQgb2RkLCBzaW5jZSBzZXRfcGFyZW50KCkgaXMgdGhlcmUgdG8sIGFz IGl0cyBuYW1lIGltcGxpZXMsCj4gPiBjaGFuZ2UgdGhlIHBhcmVudCBvZiBhIGNsb2NrLiBIb3dl dmVyLCB0aGUgbW9zdCBsaWtlbHkgY2FuZGlkYXRlIHRvCj4gPiB0cmlnZ2VyIHRoYXQgcGFyZW50 IGNoYW5nZSBpcyBhIGNhbGwgdG8gY2xrX3NldF9yYXRlKCksIHdpdGgKPiA+IGRldGVybWluZV9y YXRlKCkgZmlndXJpbmcgb3V0IHdoaWNoIHBhcmVudCBpcyB0aGUgYmVzdCBzdWl0ZWQgZm9yIGEK PiA+IGdpdmVuIHJhdGUuCj4gPgo+ID4gVGhlIG90aGVyIHRyaWdnZXIgd291bGQgYmUgYSBjYWxs IHRvIGNsa19zZXRfcGFyZW50KCksIGJ1dCBpdCdzIGZhciBsZXNzCj4gPiB1c2VkLCBhbmQgaXQg ZG9lc24ndCBsb29rIGxpa2UgdGhlcmUncyBhbnkgb2J2aW91cyB1c2VyIGZvciB0aGF0IGNsb2Nr Lgo+ID4KPiA+IFNvLCB0aGUgc2V0X3BhcmVudCBob29rIGlzIGVmZmVjdGl2ZWx5IHVudXNlZCwg cG9zc2libHkgYmVjYXVzZSBvZiBhbgo+ID4gb3ZlcnNpZ2h0LiBIb3dldmVyLCBpdCBjb3VsZCBh bHNvIGJlIGFuIGV4cGxpY2l0IGRlY2lzaW9uIGJ5IHRoZQo+ID4gb3JpZ2luYWwgYXV0aG9yIHRv IGF2b2lkIGFueSByZXBhcmVudGluZyBidXQgdGhyb3VnaCBhbiBleHBsaWNpdCBjYWxsIHRvCj4g PiBjbGtfc2V0X3BhcmVudCgpLgo+ID4KPiA+IFRoZSBsYXR0ZXIgY2FzZSB3b3VsZCBiZSBlcXVp dmFsZW50IHRvIHNldHRpbmcgdGhlIGZsYWcKPiA+IENMS19TRVRfUkFURV9OT19SRVBBUkVOVCwg dG9nZXRoZXIgd2l0aCBzZXR0aW5nIG91ciBkZXRlcm1pbmVfcmF0ZSBob29rCj4gPiB0byBfX2Ns a19tdXhfZGV0ZXJtaW5lX3JhdGUoKS4gSW5kZWVkLCBpZiBubyBkZXRlcm1pbmVfcmF0ZQo+ID4g aW1wbGVtZW50YXRpb24gaXMgcHJvdmlkZWQsIGNsa19yb3VuZF9yYXRlKCkgKHRocm91Z2gKPiA+ IGNsa19jb3JlX3JvdW5kX3JhdGVfbm9sb2NrKCkpIHdpbGwgY2FsbCBpdHNlbGYgb24gdGhlIHBh cmVudCBpZgo+ID4gQ0xLX1NFVF9SQVRFX1BBUkVOVCBpcyBzZXQsIGFuZCB3aWxsIG5vdCBjaGFu Z2UgdGhlIGNsb2NrIHJhdGUKPiA+IG90aGVyd2lzZS4gX19jbGtfbXV4X2RldGVybWluZV9yYXRl KCkgaGFzIHRoZSBleGFjdCBzYW1lIGJlaGF2aW9yIHdoZW4KPiA+IENMS19TRVRfUkFURV9OT19S RVBBUkVOVCBpcyBzZXQuCj4gPgo+ID4gQW5kIGlmIGl0IHdhcyBhbiBvdmVyc2lnaHQsIHRoZW4g d2UgYXJlIGF0IGxlYXN0IGV4cGxpY2l0IGFib3V0IG91cgo+ID4gYmVoYXZpb3Igbm93IGFuZCBp dCBjYW4gYmUgZnVydGhlciByZWZpbmVkIGRvd24gdGhlIGxpbmUuCj4gPgo+ID4gU2lnbmVkLW9m Zi1ieTogTWF4aW1lIFJpcGFyZCA8bWF4aW1lQGNlcm5vLnRlY2g+ICAKPiAKPiBMR1RNLCBzbwo+ IFJldmlld2VkLWJ5OiBHZWVydCBVeXR0ZXJob2V2ZW4gPGdlZXJ0K3JlbmVzYXNAZ2xpZGVyLmJl PgoKSSBzZWFyY2hlZCBmb3IgJ3Bvc3NpYmxlIGNhbGxlcnMnLCBJIGRpZG4ndCBmaW5kIGFueSBw bGFjZXMKd2hlcmUgdGhpcyB3b3VsZCBiZSB1c2VkIG9uIHRoZSBjb25zdW1lciBzaWRlLiBIb3dl dmVyLCBkb3duc3RyZWFtLAp0aGVyZSBpcyBhIHJ6bjEtY2xvY2stYml0c2VsZWN0LmMgY2xvY2sg ZHJpdmVyIHdoaWNoIHN0YXRlczoKCisgKiBUaGlzIGNsb2NrIHByb3ZpZGVyIGhhbmRsZXMgdGhl IGNhc2Ugb2YgdGhlIFJaTjEgd2hlcmUgeW91IGhhdmUgcGVyaXBoZXJhbHMKKyAqIHRoYXQgaGF2 ZSB0d28gcG90ZW50aWFsIGNsb2NrIHNvdXJjZSBhbmQgdHdvIGdhdGVzLCBvbmUgZm9yIGVhY2gg b2YgdGhlCisgKiBjbG9jayBzb3VyY2UgLSB0aGUgdXNlZCBjbG9jayBzb3VyY2UgKGZvciBhbGwg c3ViIGNsb2NrcykgaXMgc2VsZWN0ZWQgYnkgYQorICogc2luZ2xlIGJpdC4KKyAqIFRoYXQgc2lu Z2xlIGJpdCBhZmZlY3RzIGFsbCBzdWItY2xvY2tzLCBhbmQgdGhlcmVmb3JlIG5lZWRzIHRvIGNo YW5nZSB0aGUKKyAqIGFjdGl2ZSBnYXRlIChhbmQgdHVybiB0aGUgb3RoZXJzIG9mZikgYW5kIGZv cmNlIGEgcmVjYWxjdWxhdGlvbiBvZiB0aGUgcmF0ZXMuCgpJIGRvbid0IGtub3cgaG93IG11Y2gg b2YgdGhpcyBmaWxlIGhhcyBiZWVuIHVwc3RyZWFtZWQgKHVuZGVyIGEKZGlmZmVyZW50IGZvcm0p IGJ1dCB0aGlzIG1pZ2h0IHZlcnkgd2VsbCBiZSByZWxhdGVkIHRvIHRoZSBmYWN0IHRoYXQKcmVw YXJlbnRpbmcgaW4gc29tZSBjYXNlcyB3b3VsZCBiZSBhIG1ham9yIGlzc3VlIGFuZCB0aHVzIG5l ZWRzIHRvIGJlCmF2b2lkZWQgdW5sZXNzIGRvbmUgb24gcHVycG9zZSAoZ3Vlc3Npbmc/KS4KCk1h eWJlIFJhbHBoIGNhbiBjb21tZW50LCBidXQgZm9yIHdoYXQgSSB1bmRlcnN0YW5kLAoKUmV2aWV3 ZWQtYnk6IE1pcXVlbCBSYXluYWwgPG1pcXVlbC5yYXluYWxAYm9vdGxpbi5jb20+Cgo+IEJ1dCBJ IGRvIG5vdCBoYXZlIHRoZSBoYXJkd2FyZS4KPiAKPiA+IC0tLSBhL2RyaXZlcnMvY2xrL3JlbmVz YXMvcjlhMDZnMDMyLWNsb2Nrcy5jCj4gPiArKysgYi9kcml2ZXJzL2Nsay9yZW5lc2FzL3I5YTA2 ZzAzMi1jbG9ja3MuYwo+ID4gQEAgLTExMjEsNiArMTEyMSw3IEBAIHN0YXRpYyBpbnQgcjlhMDZn MDMyX2Nsa19tdXhfc2V0X3BhcmVudChzdHJ1Y3QgY2xrX2h3ICpodywgdTggaW5kZXgpCj4gPiAg fQo+ID4KPiA+ICBzdGF0aWMgY29uc3Qgc3RydWN0IGNsa19vcHMgY2xrX2JpdHNlbGVjdF9vcHMg PSB7Cj4gPiArICAgICAgIC5kZXRlcm1pbmVfcmF0ZSA9IF9fY2xrX211eF9kZXRlcm1pbmVfcmF0 ZSwKPiA+ICAgICAgICAgLmdldF9wYXJlbnQgPSByOWEwNmcwMzJfY2xrX211eF9nZXRfcGFyZW50 LAo+ID4gICAgICAgICAuc2V0X3BhcmVudCA9IHI5YTA2ZzAzMl9jbGtfbXV4X3NldF9wYXJlbnQs Cj4gPiAgfTsKPiA+IEBAIC0xMTQ1LDcgKzExNDYsNyBAQCByOWEwNmcwMzJfcmVnaXN0ZXJfYml0 c2VsKHN0cnVjdCByOWEwNmcwMzJfcHJpdiAqY2xvY2tzLAo+ID4KPiA+ICAgICAgICAgaW5pdC5u YW1lID0gZGVzYy0+bmFtZTsKPiA+ICAgICAgICAgaW5pdC5vcHMgPSAmY2xrX2JpdHNlbGVjdF9v cHM7Cj4gPiAtICAgICAgIGluaXQuZmxhZ3MgPSBDTEtfU0VUX1JBVEVfUEFSRU5UOwo+ID4gKyAg ICAgICBpbml0LmZsYWdzID0gQ0xLX1NFVF9SQVRFX1BBUkVOVCB8IENMS19TRVRfUkFURV9OT19S RVBBUkVOVDsKPiA+ICAgICAgICAgaW5pdC5wYXJlbnRfbmFtZXMgPSBuYW1lczsKPiA+ICAgICAg ICAgaW5pdC5udW1fcGFyZW50cyA9IDI7Cj4gPiAgCj4gCj4gR3J7b2V0amUsZWV0aW5nfXMsCj4g Cj4gICAgICAgICAgICAgICAgICAgICAgICAgR2VlcnQKPiAKClRoYW5rcywKTWlxdcOobAoKLS0g CmxpbnV4LXBoeSBtYWlsaW5nIGxpc3QKbGludXgtcGh5QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0 cHM6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcGh5Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35F0CC77B6F for ; Tue, 11 Apr 2023 13:17:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 75D2610E228; Tue, 11 Apr 2023 13:17:20 +0000 (UTC) Received: from mslow1.mail.gandi.net (mslow1.mail.gandi.net [217.70.178.240]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1B8B10E228 for ; Tue, 11 Apr 2023 13:17:17 +0000 (UTC) Received: from relay7-d.mail.gandi.net (unknown [217.70.183.200]) by mslow1.mail.gandi.net (Postfix) with ESMTP id A951DCB1FF for ; Tue, 11 Apr 2023 13:09:53 +0000 (UTC) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8667320007; Tue, 11 Apr 2023 13:09:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1681218585; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zj1JtAKrv3GVkrzExsf9B7vpxAMSpGNgfjgQje0eTak=; b=oNG2Rb7etLGd3op/Iz2fmq0xokA2awaHaTUwmpMIqfWRcdiVNffJhH1OiD/NJa8U8VhbyA yF9MXtYH8Fxz3M+cAq/7V/oq1xoDx4mXB50I/MCViACuf5Xj/3sm+jiFSUhQyd/GFiKSU+ MvbhXoQ5xcQFvUgIZ6glZLEM1HPSvT3ZkSE8cIw3GiRKuf3ey7u+ch+9vo/URZlNg8hBkX sdQ/9ZojYLUArwz1K4ERP3d5/cBFRF6/83yyqSdXppNVR0gRdgwuMipAeMDZ8IGKN7s335 n6r/K2t/A0PaaBtBH3FUkAWJV3CrDikEbkeZlUHa/BD6XrUBmGFFsgVYyetBaQ== Date: Tue, 11 Apr 2023 15:09:30 +0200 From: Miquel Raynal To: Geert Uytterhoeven Subject: Re: [PATCH v3 28/65] clk: renesas: r9a06g032: Add a determine_rate hook Message-ID: <20230411150930.4fb22d7e@xps-13> In-Reply-To: References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> <20221018-clk-range-checks-fixes-v3-28-9a1358472d52@cerno.tech> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Belloni , Prashant Gaikwad , Herve Codina , Geert Uytterhoeven , Michael Turquette , Sekhar Nori , Alexandre Torgue , dri-devel@lists.freedesktop.org, Liam Girdwood , Paul Cercueil , Max Filippov , Thierry Reding , linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Abel Vesa , Kishon Vijay Abraham I , Samuel Holland , Takashi Iwai , linux-tegra@vger.kernel.org, Jernej Skrabec , Jonathan Hunter , Chen-Yu Tsai , NXP Linux Team , Orson Zhai , Ulf Hansson , linux-mips@vger.kernel.org, Luca Ceresoli , linux-rtc@vger.kernel.org, Charles Keepax , David Lechner , alsa-devel@alsa-project.org, Manivannan Sadhasivam , linux-kernel@vger.kernel.org, Sascha Hauer , linux-actions@lists.infradead.org, Gareth Williams , Richard Fitzgerald , Mark Brown , linux-mediatek@lists.infradead.org, Maxime Ripard , Baolin Wang , Matthias Brugger , Jaroslav Kysela , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Alessandro Zummo , Maxime Coquelin , linux-sunxi@lists.linux.dev, Ralph Siemsen , Stephen Boyd , patches@opensource.cirrus.com, Peter De Schrijver , linux-stm32@st-md-mailman.stormreply.com, Nicolas Ferre , Andreas =?UTF-8?B?RsOkcmJlcg==?= , linux-renesas-soc@vger.kernel.org, Dinh Nguyen , Vinod Koul , Pengutronix Kernel Team , Chunyan Zhang , Shawn Guo , Claudiu Beznea Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Geert & Maxime, geert@linux-m68k.org wrote on Tue, 11 Apr 2023 12:27:38 +0200: > CC Gareth, Herv=C3=A9, Miquel, Ralph >=20 > On Tue, Apr 4, 2023 at 2:44=E2=80=AFPM Maxime Ripard = wrote: > > The Renesas r9a06g032 bitselect clock implements a mux with a set_parent > > hook, but doesn't provide a determine_rate implementation. > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > change the parent of a clock. However, the most likely candidate to > > trigger that parent change is a call to clk_set_rate(), with > > determine_rate() figuring out which parent is the best suited for a > > given rate. > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > used, and it doesn't look like there's any obvious user for that clock. > > > > So, the set_parent hook is effectively unused, possibly because of an > > oversight. However, it could also be an explicit decision by the > > original author to avoid any reparenting but through an explicit call to > > clk_set_parent(). > > > > The latter case would be equivalent to setting the flag > > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook > > to __clk_mux_determine_rate(). Indeed, if no determine_rate > > implementation is provided, clk_round_rate() (through > > clk_core_round_rate_nolock()) will call itself on the parent if > > CLK_SET_RATE_PARENT is set, and will not change the clock rate > > otherwise. __clk_mux_determine_rate() has the exact same behavior when > > CLK_SET_RATE_NO_REPARENT is set. > > > > And if it was an oversight, then we are at least explicit about our > > behavior now and it can be further refined down the line. > > > > Signed-off-by: Maxime Ripard =20 >=20 > LGTM, so > Reviewed-by: Geert Uytterhoeven I searched for 'possible callers', I didn't find any places where this would be used on the consumer side. However, downstream, there is a rzn1-clock-bitselect.c clock driver which states: + * This clock provider handles the case of the RZN1 where you have periphe= rals + * that have two potential clock source and two gates, one for each of the + * clock source - the used clock source (for all sub clocks) is selected b= y a + * single bit. + * That single bit affects all sub-clocks, and therefore needs to change t= he + * active gate (and turn the others off) and force a recalculation of the = rates. I don't know how much of this file has been upstreamed (under a different form) but this might very well be related to the fact that reparenting in some cases would be a major issue and thus needs to be avoided unless done on purpose (guessing?). Maybe Ralph can comment, but for what I understand, Reviewed-by: Miquel Raynal > But I do not have the hardware. >=20 > > --- a/drivers/clk/renesas/r9a06g032-clocks.c > > +++ b/drivers/clk/renesas/r9a06g032-clocks.c > > @@ -1121,6 +1121,7 @@ static int r9a06g032_clk_mux_set_parent(struct cl= k_hw *hw, u8 index) > > } > > > > static const struct clk_ops clk_bitselect_ops =3D { > > + .determine_rate =3D __clk_mux_determine_rate, > > .get_parent =3D r9a06g032_clk_mux_get_parent, > > .set_parent =3D r9a06g032_clk_mux_set_parent, > > }; > > @@ -1145,7 +1146,7 @@ r9a06g032_register_bitsel(struct r9a06g032_priv *= clocks, > > > > init.name =3D desc->name; > > init.ops =3D &clk_bitselect_ops; > > - init.flags =3D CLK_SET_RATE_PARENT; > > + init.flags =3D CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; > > init.parent_names =3D names; > > init.num_parents =3D 2; > > =20 >=20 > Gr{oetje,eeting}s, >=20 > Geert >=20 Thanks, Miqu=C3=A8l