Re: [PATCH 1/7] dt-bindings: dma: dma40: Prefer to pass sram through phandle

From: Rob Herring <robh@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/7] dt-bindings: dma: dma40: Prefer to pass sram through phandle
Date: Tue, 18 Apr 2023 17:41:46 -0500	[thread overview]
Message-ID: <20230418224146.GA2453289-robh@kernel.org> (raw)
In-Reply-To: <20230417-ux500-dma40-cleanup-v1-1-b26324956e47@linaro.org>

On Mon, Apr 17, 2023 at 09:55:46AM +0200, Linus Walleij wrote:
> Extend the DMA40 bindings so that we can pass two SRAM
> segments as phandles instead of directly referring to the
> memory address in the second reg cell. This enables more
> granular control over the SRAM, and adds the optiona LCLA
> SRAM segment as well.
> 
> Deprecate the old way of passing LCPA as a second reg cell,
> make sram compulsory.
> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  .../devicetree/bindings/dma/stericsson,dma40.yaml  | 35 +++++++++++++++++-----
>  1 file changed, 27 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
> index 64845347f44d..4fe0df937171 100644
> --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
> +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
> @@ -112,14 +112,23 @@ properties:
>        - const: stericsson,dma40
>  
>    reg:
> -    items:
> -      - description: DMA40 memory base
> -      - description: LCPA memory base
> +    oneOf:
> +      - items:
> +          - description: DMA40 memory base
> +      - items:
> +          - description: DMA40 memory base
> +          - description: LCPA memory base, deprecated, use eSRAM pool instead
> +        deprecated: true
> +
>  
>    reg-names:
> -    items:
> -      - const: base
> -      - const: lcpa
> +    oneOf:
> +      - items:
> +          - const: base
> +      - items:
> +          - const: base
> +          - const: lcpa
> +        deprecated: true
>  
>    interrupts:
>      maxItems: 1
> @@ -127,6 +136,14 @@ properties:
>    clocks:
>      maxItems: 1
>  
> +  sram:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'

Drop quotes.

> +    items:
> +      maxItems: 2

phandle-array really means phandle+args array. So the inner size is 1 
plus number of arg cells. Since you have no arg cells, that would be:

maxItems: 2
items:
  maxItems: 1

> +    description:
> +      List of phandles for the SRAM used by the DMA40 block, the first
> +      phandle is the LCPA memory, the second is the LCLA memory.
> +
>    memcpy-channels:
>      $ref: /schemas/types.yaml#/definitions/uint32-array
>      description: Array of u32 elements indicating which channels on the DMA
> @@ -138,6 +155,7 @@ required:
>    - reg
>    - interrupts
>    - clocks
> +  - sram
>    - memcpy-channels
>  
>  additionalProperties: false
> @@ -149,8 +167,9 @@ examples:
>      #include <dt-bindings/mfd/dbx500-prcmu.h>
>      dma-controller@801c0000 {
>          compatible = "stericsson,db8500-dma40", "stericsson,dma40";
> -        reg = <0x801c0000 0x1000>, <0x40010000 0x800>;
> -        reg-names = "base", "lcpa";
> +        reg = <0x801c0000 0x1000>;
> +        reg-names = "base";
> +        sram = <&lcpa>, <&lcla>;
>          interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>          #dma-cells = <3>;
>          memcpy-channels = <56 57 58 59 60>;
> 
> -- 
> 2.39.2
> 