From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1ppQTq-0008AQ-Qj for mharc-qemu-riscv@gnu.org; Thu, 20 Apr 2023 05:21:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ppQTe-0007zB-Ul for qemu-riscv@nongnu.org; Thu, 20 Apr 2023 05:21:21 -0400 Received: from mail-oo1-xc36.google.com ([2607:f8b0:4864:20::c36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ppQTd-00071f-9J for qemu-riscv@nongnu.org; Thu, 20 Apr 2023 05:21:18 -0400 Received: by mail-oo1-xc36.google.com with SMTP id 006d021491bc7-541b60e2647so333436eaf.1 for ; Thu, 20 Apr 2023 02:21:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681982476; x=1684574476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MpwTOcvXcDb7wgT7VakMT9NLz9/YlMNL0gsgkM3JNck=; b=I7RRVI9mhYjon3bSdGjbBhZZqEgzOFVCrnB6JELtiYVqSyUjspGCtFoX0Dg5c2hoFI uI9pA/9QJp0OZleCT+8P0WCXQxfHCB4+yAHyRsmelD0bU4pZ+88n5R3jf4fQ1FlXaqZf NxtoXTLrLq78DlXM6fBKH/qZ7ZRA6pImtjxk6gl9icf4YNRTLMPwk4jxPRJVYNBYEHKi wEliN4NDn11CK9KyX0Vmz3OYF/N9KjgMOd0OAniKVhiFYUbu6Xwbrjeye1/NurV1ucgT 873JaDZ68Zp6rvFnjgaucuUTo+SCSi5tDkXSfG/CcYqF5XpznJmTtXNBwFY1s/nTgLHd LTJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681982476; x=1684574476; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MpwTOcvXcDb7wgT7VakMT9NLz9/YlMNL0gsgkM3JNck=; b=DsBkeVMqwsZWZr7bUeX0sfAY501xiJi5PIQ37qEGhP5v8vHUbsdenXwy/33qdkt2Ca KowIjsExvn+k3ln76erIB3qItugdr6g5DRK8mw6pn1g8zakIKKnQDidnxaqDWkNs+nTW Br9mFmmiKOBigYzVb2XLbnbyFPs3FvfAhSIaZKASDo4/T5QqlTI24Jlv5JiDC1qbg6jm ggKskeTJwwxYwjRH5i+SWHd+XVBrBO/2sbwBrYtP7pEmN0Vb25miCEEv+Cl/VXOdAs01 fMuzk2iL0kd5W6j9XKfqSS7QQD8pZ0W1LirR78r0wQSLScDfRMir/VSQS/hOyIHp5nsd e+vg== X-Gm-Message-State: AAQBX9fG1snm7gmy2oQYq3mtE7yA+tx41+0l+vuGXH+w2o9tVsjik/1H 8mGYlbMGfwVQIM5B0rqTFFfs2A== X-Google-Smtp-Source: AKy350YyO//IXhtR7QTb/ggaBu4OhCK+mZ2e3Vks+PwHd5VPbs02yFZyn9Y9O09IB7d0f8NoMo0LGA== X-Received: by 2002:a05:6870:d1c7:b0:17a:e21f:4aa4 with SMTP id b7-20020a056870d1c700b0017ae21f4aa4mr682075oac.31.1681982476228; Thu, 20 Apr 2023 02:21:16 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([191.255.108.232]) by smtp.gmail.com with ESMTPSA id t1-20020a056870e74100b0017280f7d653sm529668oak.35.2023.04.20.02.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 02:21:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH RESEND v7 03/12] target/riscv/cpu.c: remove set_priv_version() Date: Thu, 20 Apr 2023 06:20:51 -0300 Message-Id: <20230420092100.177464-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230420092100.177464-1-dbarboza@ventanamicro.com> References: <20230420092100.177464-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Apr 2023 09:21:21 -0000 The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fed7b467e4..bec60fe585 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -247,11 +247,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) env->misa_ext_mask = env->misa_ext = ext; } -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver = priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -350,7 +345,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; } #if defined(TARGET_RISCV64) @@ -361,7 +356,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -371,7 +366,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -383,7 +378,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -396,7 +391,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.ext_zfh = true; cpu->cfg.mmu = true; @@ -430,7 +425,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -443,7 +438,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -453,7 +448,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -465,7 +460,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -478,7 +473,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -492,7 +487,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1174,7 +1169,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (priv_version >= PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver = priv_version; } riscv_cpu_validate_misa_priv(env, &local_err); -- 2.40.0