* [RFC RESEND 0/3] Add support control UP board CPLD/FPGA pin control
@ 2023-04-25 15:21 larry.lai
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: larry.lai @ 2023-04-25 15:21 UTC (permalink / raw)
To: lee, andriy.shevchenko, linus.walleij, pavel
Cc: linux-kernel, linux-gpio, linux-leds, GaryWang, musa.lin,
jack.chang, noah.hung, michael.wang, larry.lai
The UP board <https://up-board.org/> is the computer board for
Professional Makers and Industrial Applications. We want to upstream
the UP board 40-pin GP-bus Kernel driver for giving the users better
experience on the software release. (not just download from UP board
github)
These patches are generated from the Linux kernel mainline tag v6.0.
This is the RFC PATCH resend and fixed some of the review issues from
Andy Shevchenko, Lee Jones reviewed on 2022/12/08.
larry.lai (3):
mfd: Add support for UP board CPLD/FPGA
pinctrl: Add support pin control for UP board CPLD/FPGA
leds: Add support for UP board CPLD onboard LEDS
drivers/leds/Kconfig | 10 +
drivers/leds/Makefile | 1 +
drivers/leds/leds-upboard.c | 79 ++
drivers/mfd/Kconfig | 12 +
drivers/mfd/Makefile | 1 +
drivers/mfd/upboard-fpga.c | 527 ++++++++++++
drivers/pinctrl/Kconfig | 14 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-upboard.c | 1281 +++++++++++++++++++++++++++++
include/linux/mfd/upboard-fpga.h | 61 ++
10 files changed, 1987 insertions(+)
create mode 100644 drivers/leds/leds-upboard.c
create mode 100644 drivers/mfd/upboard-fpga.c
create mode 100644 drivers/pinctrl/pinctrl-upboard.c
create mode 100644 include/linux/mfd/upboard-fpga.h
base-commit: 4fe89d07dcc2804c8b562f6c7896a45643d34b2f
--
2.17.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
2023-04-25 15:21 [RFC RESEND 0/3] Add support control UP board CPLD/FPGA pin control larry.lai
@ 2023-04-25 15:21 ` larry.lai
2023-04-27 17:14 ` Lee Jones
` (2 more replies)
2023-04-25 15:21 ` [RFC RESEND 2/3] pinctrl: Add support pin control " larry.lai
2023-04-25 15:21 ` [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS larry.lai
2 siblings, 3 replies; 9+ messages in thread
From: larry.lai @ 2023-04-25 15:21 UTC (permalink / raw)
To: lee, andriy.shevchenko, linus.walleij, pavel
Cc: linux-kernel, linux-gpio, linux-leds, GaryWang, musa.lin,
jack.chang, noah.hung, michael.wang, larry.lai, Javier Arteaga,
Nicola Lunghi
The UP Squared board <http://www.upboard.com> implements certain
features (pin control, onboard LEDs or CEC) through an on-board CPLD/FPGA.
This mfd driver implements the line protocol to read and write registers
from the FPGA through regmap. The register address map is also included.
The UP Boards provide a few I/O pin headers (for both GPIO and
functions), including a 40-pin Raspberry Pi compatible header.
This patch implements support for the FPGA-based pin controller that
manages direction and enable state for those header pins.
Partial support UP boards:
* UP core + CREX
* UP core + CRST02
Signed-off-by: Javier Arteaga <javier@emutex.com>
[merge various fixes]
Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
Reviewed-by: Lee Jones <lee@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
---
RFC 2022/11/23 -> RFC 2023/04/25
(1) Refer 2022/12/08 Andy Shevchenko review, cleaned up coding style
and addressed review comments.
PATCH V3 -> RFC 2022/11/23:
(1) Refer 2022/11/16 Lee Jones review, cleaned up coding style and
addressed review comments.
(2) Description on the UP Boards FPGA register read/write protocols
PATCH V2 -> V3:
(1) fixed kernel test robot compiler warning
PATCH V1 -> V2:
(1) Synchronizing upboard github to rc2
(2) Refer 2022/10/31 Lee Jones review, fixed some of the issues.
---
---
drivers/mfd/Kconfig | 12 +
drivers/mfd/Makefile | 1 +
drivers/mfd/upboard-fpga.c | 527 +++++++++++++++++++++++++++++++
include/linux/mfd/upboard-fpga.h | 61 ++++
4 files changed, 601 insertions(+)
create mode 100644 drivers/mfd/upboard-fpga.c
create mode 100644 include/linux/mfd/upboard-fpga.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index abb58ab1a1a4..1041e937fc7a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2104,6 +2104,18 @@ config MFD_QCOM_PM8008
under it in the device tree. Additional drivers must be enabled in
order to use the functionality of the device.
+config MFD_INTEL_UPBOARD_FPGA
+ tristate "Support for the Intel platform foundation kit UP board FPGA"
+ select MFD_CORE
+ depends on X86 && ACPI
+ help
+ Select this option to enable the Intel AAEON UP and UP^2 on-board FPGA.
+ This is core driver for the UP board that implements certain (pin
+ control, onboard LEDs or CEC) through an on-board FPGA.
+
+ To compile this driver as a module, choose M here: the module will be
+ called upboard-fpga.
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 858cacf659d6..8374a05f6f43 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -250,6 +250,7 @@ obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
obj-$(CONFIG_MFD_ALTERA_SYSMGR) += altera-sysmgr.o
obj-$(CONFIG_MFD_STPMIC1) += stpmic1.o
obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o
+obj-$(CONFIG_MFD_INTEL_UPBOARD_FPGA) += upboard-fpga.o
obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o
obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
diff --git a/drivers/mfd/upboard-fpga.c b/drivers/mfd/upboard-fpga.c
new file mode 100644
index 000000000000..85fd0f858781
--- /dev/null
+++ b/drivers/mfd/upboard-fpga.c
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UP Board multi function device driver for control CPLD/FPGA to
+ * provide more GPIO driving power also provide CPLD LEDs and pin mux function
+ * recognize HID AANT0F00 ~ AAANT0F04 in ACPI name space
+ *
+ * Copyright (c) AAEON. All rights reserved.
+ *
+ * Author: Gary Wang <garywang@aaeon.com.tw>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/dmi.h>
+#include <linux/gpio/consumer.h>
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/upboard-fpga.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/bits.h>
+#include <linux/err.h>
+
+struct upboard_fpga_data {
+ const struct regmap_config *cpld_config;
+ const struct mfd_cell *cells;
+ size_t ncells;
+};
+
+#define AAEON_MANUFACTURER_ID 0x01
+#define SUPPORTED_FW_MAJOR 0x0
+#define MENUFACTURER_ID_MASK GENMASK(7, 0)
+
+#define FIRMWARE_ID_BUILD_OFFSET (12)
+#define FIRMWARE_ID_MAJOR_OFFSET (8)
+#define FIRMWARE_ID_MINOR_OFFSET (4)
+#define FIRMWARE_ID_PATCH_OFFSET (0)
+#define FIRMWARE_ID_MASK GENMASK(3, 0)
+
+/*
+ * For UP Board Series FPGA register read/write protocols
+ * EMUTEX specs:
+ * D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 .... D22 D23
+ * [RW][ address ][ DATA ]
+ *
+ * Read Sequence:
+ * ___ ____________________________________________________ _________
+ * clr: \_/ <--low-pulse does start the write-readback \_/<--start
+ * sequence with partital reset of internal new sequence
+ * registers but the CONF-REG.
+ * ____________________________________________________________________
+ * rst: _/ _ _ _ _ _ _ __ __ __ _
+ * stb: STB#1->_/1\_/2\_/3\_...._/7\_/8\_/9\_/10\_..../23\_/24\_/<-STB#25 edge
+ * is needed
+ * to ACK
+ * (D0 - D7 stb rising latch)
+ * data_in: D0 D1 D2 .... D6 D7 don't ........ care(DC)
+ * data_out: don't ...........care(DC) D8 D9 .... D22 D23
+ * (D8 - D23 stb falling latch)
+ * flag_Read: _________...._________
+ * __DC_ ____________...._________/ \_
+ * counter:
+ * [00]DC[00][01][02] ............[08][9][10]............[24][00]
+ * CONF-REG:
+ * [00] [ CONF-REG ]
+ * wreg:
+ * [00]DC[00][ wreg=SHFT(wreg) ][ADR][DATA][wreg=SHFT(wreg)]
+ * wreg2:
+ * [ (COPY)=ADDR ]
+ */
+static int upboard_fpga_read(void *context, unsigned int reg, unsigned int *val)
+{
+ struct upboard_fpga * const fpga = context;
+ int i;
+
+ gpiod_set_value(fpga->clear_gpio, 0);
+ gpiod_set_value(fpga->clear_gpio, 1);
+
+ reg |= UPFPGA_READ_FLAG;
+
+ for (i = UPFPGA_ADDRESS_SIZE; i >= 0; i--) {
+ gpiod_set_value(fpga->strobe_gpio, 0);
+ gpiod_set_value(fpga->datain_gpio, !!(reg & BIT(i)));
+ gpiod_set_value(fpga->strobe_gpio, 1);
+ }
+
+ gpiod_set_value(fpga->strobe_gpio, 0);
+ *val = 0;
+
+ for (i = UPFPGA_REGISTER_SIZE - 1; i >= 0; i--) {
+ gpiod_set_value(fpga->strobe_gpio, 1);
+ gpiod_set_value(fpga->strobe_gpio, 0);
+ *val |= gpiod_get_value(fpga->dataout_gpio) << i;
+ }
+
+ gpiod_set_value(fpga->strobe_gpio, 1);
+
+ return 0;
+}
+
+/*
+ * Write Sequence:
+ * ___ ____________________________________________________ _________
+ * clr: \_/ <--low-pulse does start the write-readback \_/<--start
+ * sequence with partital reset of internal new sequence
+ * registers but the CONF-REG.
+ * ____________________________________________________________________
+ * rst: _/ _ _ _ _ _ _ __ __ __ _
+ * stb: STB#1->_/1\_/2\_/3\_...._/7\_/8\_/9\_/10\_..../23\_/24\_/<-STB#25 edge
+ * is needed
+ * to ACK
+ * (D0 - D23 stb rising latch)
+ * data_in: D0 D1 D2 .... D6 D7 D8 D9 .... D22 D23
+ * data_out: don't ................................care (DC)
+ * flag_Read:
+ * __DC_ ____________....__________________________________
+ * counter:
+ * [00]DC[00][01][02] ............[08][9][10]............[24][00]
+ * wreg:
+ * [00]DC[00][wreg=SHFT(wreg)&dat_in ][SHFT(wreg)&dat_in][DAT]
+ * wreg2:
+ * [ (COPY)=ADDR ]
+ * CONF-REG:
+ * [00] [ CONF-REG = OLD VALUE ][CONF-REG=DAT]
+ */
+static int upboard_fpga_write(void *context, unsigned int reg, unsigned int val)
+{
+ struct upboard_fpga * const fpga = context;
+ int i;
+
+ gpiod_set_value(fpga->clear_gpio, 0);
+ gpiod_set_value(fpga->clear_gpio, 1);
+
+ for (i = UPFPGA_ADDRESS_SIZE; i >= 0; i--) {
+ gpiod_set_value(fpga->strobe_gpio, 0);
+ gpiod_set_value(fpga->datain_gpio, !!(reg & BIT(i)));
+ gpiod_set_value(fpga->strobe_gpio, 1);
+ }
+
+ gpiod_set_value(fpga->strobe_gpio, 0);
+
+ for (i = UPFPGA_REGISTER_SIZE - 1; i >= 0; i--) {
+ gpiod_set_value(fpga->datain_gpio, !!(val & BIT(i)));
+ gpiod_set_value(fpga->strobe_gpio, 1);
+ gpiod_set_value(fpga->strobe_gpio, 0);
+ }
+
+ gpiod_set_value(fpga->strobe_gpio, 1);
+
+ return 0;
+}
+
+static const struct regmap_range upboard_up_readable_ranges[] = {
+ regmap_reg_range(UPFPGA_REG_PLATFORM_ID, UPFPGA_REG_FIRMWARE_ID),
+ regmap_reg_range(UPFPGA_REG_FUNC_EN0, UPFPGA_REG_FUNC_EN0),
+ regmap_reg_range(UPFPGA_REG_GPIO_DIR0, UPFPGA_REG_GPIO_DIR1),
+};
+
+static const struct regmap_range upboard_up_writable_ranges[] = {
+ regmap_reg_range(UPFPGA_REG_FUNC_EN0, UPFPGA_REG_FUNC_EN0),
+ regmap_reg_range(UPFPGA_REG_GPIO_DIR0, UPFPGA_REG_GPIO_DIR1),
+};
+
+static const struct regmap_access_table upboard_up_readable_table = {
+ .yes_ranges = upboard_up_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(upboard_up_readable_ranges),
+};
+
+static const struct regmap_access_table upboard_up_writable_table = {
+ .yes_ranges = upboard_up_writable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(upboard_up_writable_ranges),
+};
+
+static const struct regmap_config upboard_up_regmap_config = {
+ .reg_bits = UPFPGA_ADDRESS_SIZE,
+ .val_bits = UPFPGA_REGISTER_SIZE,
+ .max_register = UPFPGA_REG_MAX,
+ .reg_read = upboard_fpga_read,
+ .reg_write = upboard_fpga_write,
+ .fast_io = false,
+ .cache_type = REGCACHE_RBTREE,
+ .rd_table = &upboard_up_readable_table,
+ .wr_table = &upboard_up_writable_table,
+};
+
+static struct upboard_led_data upboard_up_led_data[] = {
+ { .bit = 0, .colour = "yellow" },
+ { .bit = 1, .colour = "green" },
+ { .bit = 2, .colour = "red" },
+};
+
+static const struct mfd_cell upboard_up_mfd_cells[] = {
+ { .name = "upboard-pinctrl" },
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up_led_data[0],
+ sizeof(*upboard_up_led_data), 0),
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up_led_data[1],
+ sizeof(*upboard_up_led_data), 1),
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up_led_data[2],
+ sizeof(*upboard_up_led_data), 2),
+};
+
+/* UP Squared 6000 EHL board */
+
+static const struct upboard_fpga_data upboard_up_fpga_data = {
+ .cpld_config = &upboard_up_regmap_config,
+ .cells = upboard_up_mfd_cells,
+ .ncells = ARRAY_SIZE(upboard_up_mfd_cells),
+};
+
+static const struct mfd_cell upboard_pinctrl_cells[] = {
+ { .name = "upboard-pinctrl" },
+};
+
+static const struct upboard_fpga_data upboard_pinctrl_data = {
+ .cpld_config = &upboard_up_regmap_config,
+ .cells = upboard_pinctrl_cells,
+ .ncells = ARRAY_SIZE(upboard_pinctrl_cells),
+};
+
+/* UP^2 board */
+static const struct regmap_range upboard_up2_readable_ranges[] = {
+ regmap_reg_range(UPFPGA_REG_PLATFORM_ID, UPFPGA_REG_FIRMWARE_ID),
+ regmap_reg_range(UPFPGA_REG_FUNC_EN0, UPFPGA_REG_FUNC_EN1),
+ regmap_reg_range(UPFPGA_REG_GPIO_EN0, UPFPGA_REG_GPIO_EN2),
+ regmap_reg_range(UPFPGA_REG_GPIO_DIR0, UPFPGA_REG_GPIO_DIR2),
+};
+
+static const struct regmap_range upboard_up2_writable_ranges[] = {
+ regmap_reg_range(UPFPGA_REG_FUNC_EN0, UPFPGA_REG_FUNC_EN1),
+ regmap_reg_range(UPFPGA_REG_GPIO_EN0, UPFPGA_REG_GPIO_EN2),
+ regmap_reg_range(UPFPGA_REG_GPIO_DIR0, UPFPGA_REG_GPIO_DIR2),
+};
+
+static const struct regmap_access_table upboard_up2_readable_table = {
+ .yes_ranges = upboard_up2_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(upboard_up2_readable_ranges),
+};
+
+static const struct regmap_access_table upboard_up2_writable_table = {
+ .yes_ranges = upboard_up2_writable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(upboard_up2_writable_ranges),
+};
+
+static const struct regmap_config upboard_up2_regmap_config = {
+ .reg_bits = UPFPGA_ADDRESS_SIZE,
+ .val_bits = UPFPGA_REGISTER_SIZE,
+ .max_register = UPFPGA_REG_MAX,
+ .reg_read = upboard_fpga_read,
+ .reg_write = upboard_fpga_write,
+ .fast_io = false,
+ .cache_type = REGCACHE_NONE,
+ .rd_table = &upboard_up2_readable_table,
+ .wr_table = &upboard_up2_writable_table,
+};
+
+static struct upboard_led_data upboard_up2_led_data[] = {
+ { .bit = 0, .colour = "blue" },
+ { .bit = 1, .colour = "yellow" },
+ { .bit = 2, .colour = "green" },
+ { .bit = 3, .colour = "red" },
+};
+
+static const struct mfd_cell upboard_up2_mfd_cells[] = {
+ { .name = "upboard-pinctrl" },
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up2_led_data[0],
+ sizeof(*upboard_up2_led_data), 0),
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up2_led_data[1],
+ sizeof(*upboard_up2_led_data), 1),
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up2_led_data[2],
+ sizeof(*upboard_up2_led_data), 2),
+ MFD_CELL_BASIC("upboard-led", NULL, &upboard_up2_led_data[3],
+ sizeof(*upboard_up2_led_data), 3),
+};
+
+static const struct upboard_fpga_data upboard_up2_fpga_data = {
+ .cpld_config = &upboard_up2_regmap_config,
+ .cells = upboard_up2_mfd_cells,
+ .ncells = ARRAY_SIZE(upboard_up2_mfd_cells),
+};
+
+/* UP-CRST02 carrier board for UP Core */
+
+/* same MAX10 config as UP2, but same LED cells as UP1 */
+static const struct upboard_fpga_data upboard_upcore_crst02_fpga_data = {
+ .cpld_config = &upboard_up2_regmap_config,
+ .cells = upboard_up_mfd_cells,
+ .ncells = ARRAY_SIZE(upboard_up_mfd_cells),
+};
+
+static int __init upboard_fpga_gpio_init(struct upboard_fpga *fpga)
+{
+ enum gpiod_flags flags = fpga->uninitialised ? GPIOD_OUT_LOW : GPIOD_ASIS;
+
+ fpga->enable_gpio = devm_gpiod_get(fpga->dev, "enable", flags);
+ if (IS_ERR(fpga->enable_gpio))
+ return PTR_ERR(fpga->enable_gpio);
+
+ fpga->clear_gpio = devm_gpiod_get(fpga->dev, "clear", GPIOD_OUT_LOW);
+ if (IS_ERR(fpga->clear_gpio))
+ return PTR_ERR(fpga->clear_gpio);
+
+ fpga->strobe_gpio = devm_gpiod_get(fpga->dev, "strobe", GPIOD_OUT_LOW);
+ if (IS_ERR(fpga->strobe_gpio))
+ return PTR_ERR(fpga->strobe_gpio);
+
+ fpga->datain_gpio = devm_gpiod_get(fpga->dev, "datain", GPIOD_OUT_LOW);
+ if (IS_ERR(fpga->datain_gpio))
+ return PTR_ERR(fpga->datain_gpio);
+
+ fpga->dataout_gpio = devm_gpiod_get(fpga->dev, "dataout", GPIOD_IN);
+ if (IS_ERR(fpga->dataout_gpio))
+ return PTR_ERR(fpga->dataout_gpio);
+
+ /*
+ * The SoC pinctrl driver may not support reserving the GPIO line for
+ * FPGA reset without causing an undesired reset pulse. This will clear
+ * any settings on the FPGA, so only do it if we must.
+ * Reset GPIO defaults HIGH, get GPIO and set to LOW, then set back to
+ * HIGH as a pulse.
+ */
+ if (fpga->uninitialised) {
+ fpga->reset_gpio = devm_gpiod_get(fpga->dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(fpga->reset_gpio))
+ return PTR_ERR(fpga->reset_gpio);
+
+ gpiod_set_value(fpga->reset_gpio, 1);
+ }
+
+ gpiod_set_value(fpga->enable_gpio, 1);
+ fpga->uninitialised = false;
+
+ return 0;
+}
+
+/*
+ * This function is for debugging with user for showing firmware information.
+ */
+static int __init upboard_fpga_show_firmware_info(struct upboard_fpga *fpga)
+{
+ unsigned int platform_id, manufacturer_id;
+ unsigned int firmware_id, build, major, minor, patch;
+ int ret;
+
+ if (!fpga)
+ return -ENOMEM;
+
+ ret = regmap_read(fpga->regmap, UPFPGA_REG_PLATFORM_ID, &platform_id);
+ if (ret)
+ return ret;
+
+ manufacturer_id = platform_id & MENUFACTURER_ID_MASK;
+ if (manufacturer_id != AAEON_MANUFACTURER_ID) {
+ dev_err(fpga->dev,
+ "driver not compatible with custom FPGA FW from manufacturer id 0x%02x. Exiting",
+ manufacturer_id);
+
+ return -ENODEV;
+ }
+
+ ret = regmap_read(fpga->regmap, UPFPGA_REG_FIRMWARE_ID, &firmware_id);
+ if (ret)
+ return ret;
+
+ build = (firmware_id >> FIRMWARE_ID_BUILD_OFFSET) & FIRMWARE_ID_MASK;
+ major = (firmware_id >> FIRMWARE_ID_MAJOR_OFFSET) & FIRMWARE_ID_MASK;
+ minor = (firmware_id >> FIRMWARE_ID_MINOR_OFFSET) & FIRMWARE_ID_MASK;
+ patch = (firmware_id >> FIRMWARE_ID_PATCH_OFFSET) & FIRMWARE_ID_MASK;
+
+ if (major != SUPPORTED_FW_MAJOR) {
+ dev_err(fpga->dev, "unsupported FPGA FW v%u.%u.%u build 0x%02x",
+ major, minor, patch, build);
+
+ return -ENODEV;
+ }
+
+ dev_info(fpga->dev, "compatible FPGA FW v%u.%u.%u build 0x%02x",
+ major, minor, patch, build);
+
+ return 0;
+}
+
+/*
+ * MFD upboard-fpga is ACPI driver and can recognize the AANT ID from different
+ * kind of upboards. We get the LED GPIO initialized information from this
+ * then add led-upboard driver.
+ */
+int upboard_led_gpio_register(struct upboard_fpga *fpga)
+{
+ struct gpio_led blue_led, yellow_led, green_led, red_led;
+ struct gpio_desc *desc;
+ static struct gpio_led upboard_gpio_leds[4];
+ int leds = 0;
+ static struct gpio_led_platform_data upboard_gpio_led_platform_data;
+ static const struct mfd_cell upboard_gpio_led_cells[] = {
+ MFD_CELL_BASIC("leds-gpio", NULL,
+ &upboard_gpio_led_platform_data,
+ sizeof(upboard_gpio_led_platform_data), 0)
+ };
+ int ret;
+
+ desc = devm_gpiod_get(fpga->dev, "blue", GPIOD_OUT_LOW);
+ if (!IS_ERR(desc)) {
+ blue_led.name = "upboard:blue:";
+ blue_led.gpio = desc_to_gpio(desc);
+ blue_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
+ upboard_gpio_leds[leds++] = blue_led;
+ devm_gpiod_put(fpga->dev, desc);
+ }
+ desc = devm_gpiod_get(fpga->dev, "yellow", GPIOD_OUT_LOW);
+ if (!IS_ERR(desc)) {
+ yellow_led.name = "upboard:yellow:";
+ yellow_led.gpio = desc_to_gpio(desc);
+ yellow_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
+ upboard_gpio_leds[leds++] = yellow_led;
+ devm_gpiod_put(fpga->dev, desc);
+ }
+ desc = devm_gpiod_get(fpga->dev, "green", GPIOD_OUT_LOW);
+ if (!IS_ERR(desc)) {
+ green_led.name = "upboard:green:";
+ green_led.gpio = desc_to_gpio(desc);
+ green_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
+ upboard_gpio_leds[leds++] = green_led;
+ devm_gpiod_put(fpga->dev, desc);
+ }
+ desc = devm_gpiod_get(fpga->dev, "red", GPIOD_OUT_LOW);
+ if (!IS_ERR(desc)) {
+ red_led.name = "upboard:red:";
+ red_led.gpio = desc_to_gpio(desc);
+ red_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
+ upboard_gpio_leds[leds++] = red_led;
+ devm_gpiod_put(fpga->dev, desc);
+ }
+
+ /* no LEDs */
+ if (leds == 0)
+ return 0;
+
+ upboard_gpio_led_platform_data.num_leds = leds;
+ upboard_gpio_led_platform_data.leds = upboard_gpio_leds;
+
+ ret = devm_mfd_add_devices(fpga->dev, PLATFORM_DEVID_AUTO,
+ upboard_gpio_led_cells,
+ ARRAY_SIZE(upboard_gpio_led_cells),
+ NULL, 0, NULL);
+ if (ret) {
+ dev_err(fpga->dev, "Failed to add GPIO LEDs", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct acpi_device_id upboard_fpga_acpi_match[] = {
+ { "AANT0000", (kernel_ulong_t)&upboard_pinctrl_data },
+ { "AANT0F00", (kernel_ulong_t)&upboard_up_fpga_data },
+ { "AANT0F01", (kernel_ulong_t)&upboard_up2_fpga_data },
+ { "AANT0F02", (kernel_ulong_t)&upboard_up_fpga_data },
+ { "AANT0F03", (kernel_ulong_t)&upboard_upcore_crst02_fpga_data },
+ { "AANT0F04", (kernel_ulong_t)&upboard_up_fpga_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, upboard_fpga_acpi_match);
+
+static int __init upboard_fpga_probe(struct platform_device *pdev)
+{
+ struct upboard_fpga *fpga;
+ const struct acpi_device_id *id;
+ const struct upboard_fpga_data *fpga_data;
+ int ret;
+ struct device *dev = &pdev->dev;
+
+ id = acpi_match_device(upboard_fpga_acpi_match, dev);
+ if (!id)
+ return -ENODEV;
+
+ fpga_data = (const struct upboard_fpga_data *) id->driver_data;
+
+ fpga = devm_kzalloc(dev, sizeof(*fpga), GFP_KERNEL);
+ if (!fpga)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, fpga);
+ fpga->regmap = devm_regmap_init(dev, NULL, fpga, fpga_data->cpld_config);
+ fpga->cpld_config = fpga_data->cpld_config;
+
+ if (IS_ERR(fpga->regmap))
+ return PTR_ERR(fpga->regmap);
+
+ ret = upboard_fpga_gpio_init(fpga);
+ if (ret) {
+ /*
+ * This is for compatiable with some upboards w/o FPGA firmware,
+ * so just showing debug info and do not return directly.
+ */
+ dev_warn(dev, "Failed to initialize FPGA common GPIOs: %d", ret);
+ } else {
+ upboard_fpga_show_firmware_info(fpga);
+ }
+
+ /* register GPIO LEDs */
+ ret = upboard_led_gpio_register(fpga);
+ if (ret) {
+ /*
+ * This is for compatiable with some upboards w/o LEDs.
+ */
+ dev_warn(dev, "Failed to register LEDs: %d", ret);
+ }
+
+ return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
+ fpga_data->cells,
+ fpga_data->ncells,
+ NULL, 0, NULL);
+}
+
+static struct platform_driver upboard_fpga_driver = {
+ .driver = {
+ .name = "upboard-fpga",
+ .acpi_match_table = upboard_fpga_acpi_match,
+ },
+};
+module_platform_driver_probe(upboard_fpga_driver, upboard_fpga_probe);
+
+MODULE_AUTHOR("Gary Wang <garywang@aaeon.com.tw>");
+MODULE_DESCRIPTION("UP Board CPLD/FPGA driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/upboard-fpga.h b/include/linux/mfd/upboard-fpga.h
new file mode 100644
index 000000000000..1fa073e5c53c
--- /dev/null
+++ b/include/linux/mfd/upboard-fpga.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UP Board CPLD/FPGA driver
+ *
+ * Copyright (c) AAEON. All rights reserved.
+ *
+ * Author: Gary Wang <garywang@aaeon.com.tw>
+ *
+ */
+
+#ifndef __LINUX_MFD_UPBOARD_FPGA_H
+#define __LINUX_MFD_UPBOARD_FPGA_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+/* CPLD/FPGA protocol version */
+#define UPFPGA_PROTOCOL_V1_HRV 1
+#define UPFPGA_PROTOCOL_V2_HRV 2
+
+#define UPFPGA_ADDRESS_SIZE 7
+#define UPFPGA_REGISTER_SIZE 16
+
+#define UPFPGA_READ_FLAG (1 << UPFPGA_ADDRESS_SIZE)
+
+enum upboard_fpgareg {
+ UPFPGA_REG_PLATFORM_ID = 0x10,
+ UPFPGA_REG_FIRMWARE_ID = 0x11,
+ UPFPGA_REG_FUNC_EN0 = 0x20,
+ UPFPGA_REG_FUNC_EN1 = 0x21,
+ UPFPGA_REG_GPIO_EN0 = 0x30,
+ UPFPGA_REG_GPIO_EN1 = 0x31,
+ UPFPGA_REG_GPIO_EN2 = 0x32,
+ UPFPGA_REG_GPIO_DIR0 = 0x40,
+ UPFPGA_REG_GPIO_DIR1 = 0x41,
+ UPFPGA_REG_GPIO_DIR2 = 0x42,
+ UPFPGA_REG_MAX,
+};
+
+struct upboard_fpga {
+ struct device *dev;
+ struct regmap *regmap;
+ struct regmap_config *cpld_config;
+ struct gpio_desc *enable_gpio;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *clear_gpio;
+ struct gpio_desc *strobe_gpio;
+ struct gpio_desc *datain_gpio;
+ struct gpio_desc *dataout_gpio;
+ bool uninitialised;
+};
+
+struct upboard_led_data {
+ unsigned int bit;
+ const char *colour;
+};
+
+bool regmap_check_writeable(struct upboard_fpga *fpga, unsigned int reg);
+int upboard_led_gpio_register(struct upboard_fpga *fpga);
+
+#endif /* __LINUX_MFD_UPBOARD_FPGA_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC RESEND 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA
2023-04-25 15:21 [RFC RESEND 0/3] Add support control UP board CPLD/FPGA pin control larry.lai
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
@ 2023-04-25 15:21 ` larry.lai
2023-05-02 17:37 ` kernel test robot
2023-04-25 15:21 ` [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS larry.lai
2 siblings, 1 reply; 9+ messages in thread
From: larry.lai @ 2023-04-25 15:21 UTC (permalink / raw)
To: lee, andriy.shevchenko, linus.walleij, pavel
Cc: linux-kernel, linux-gpio, linux-leds, GaryWang, musa.lin,
jack.chang, noah.hung, michael.wang, larry.lai
The UP Squared board <http://www.upboard.com> implements certain
features (pin control) through an on-board FPGA.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
---
RFC 2022/11/23 -> RFC 2023/04/25
(1) Refer 2022/12/08 Andy Shevchenko review, cleaned up coding style and
addressed review comments.
PATCH V3 -> RFC 2022/11/23:
(1) Refer 2022/11/09 Linus Walleij review, cleaned up coding style and
addressed review comments.
PATCH V2 -> V3:
There's no change.
PATCH V1 -> V2:
(1) Synchronized with upboard github to rc2
(2) Refer 2022/10/19 Mark Brown and Andy Shevchenko review, we removed
the regmap and acpi patches and implement in upboard pinctrl driver.
(3) Refer 2022/10/19 Andy Shevchenko review, fixed the coding style
issues, removed using gpio_xxxx API and removed including <linux/gpio.h>.
---
---
drivers/pinctrl/Kconfig | 14 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-upboard.c | 1281 +++++++++++++++++++++++++++++
3 files changed, 1296 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-upboard.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1cf74b0c42e5..cc8dae75289b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -483,6 +483,20 @@ config PINCTRL_THUNDERBAY
rate control and direction control. This module will be
called as pinctrl-thunderbay.
+config PINCTRL_UPBOARD
+ tristate "UP board FPGA pin controller"
+ depends on (X86 && ACPI) || COMPILE_TEST
+ depends on MFD_INTEL_UPBOARD_FPGA
+ select GENERIC_PINCONF
+ select PINMUX
+ select PINCONF
+ help
+ Pin controller for the FPGA GPIO lines on UP boards. Due to the
+ hardware layout, these are meant to be controlled in tandem with their
+ corresponding Intel SoC GPIOs.
+ To compile this driver as a module, choose M here: the module
+ will be called pinctrl-upboard.
+
config PINCTRL_ZYNQ
bool "Pinctrl driver for Xilinx Zynq"
depends on ARCH_ZYNQ
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e76f5cdc64b0..c366706d36e7 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_THUNDERBAY) += pinctrl-thunderbay.o
+obj-$(CONFIG_PINCTRL_UPBOARD) += pinctrl-upboard.o
obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
diff --git a/drivers/pinctrl/pinctrl-upboard.c b/drivers/pinctrl/pinctrl-upboard.c
new file mode 100644
index 000000000000..9cabbf460d6e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-upboard.c
@@ -0,0 +1,1281 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UP Board HAT pin controller driver
+ * remapping native pin to RPI pin and set CPLD pin dir
+ *
+ * Copyright (c) AAEON. All rights reserved.
+ *
+ * Authors: Gary Wang <garywang@aaeon.com.tw>
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/dmi.h>
+#include <linux/gpio/consumer.h>
+#include <linux/gpio/driver.h>
+#include <linux/kernel.h>
+#include <linux/mfd/upboard-fpga.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/interrupt.h>
+#include <linux/string.h>
+
+#include "core.h"
+#include "intel/pinctrl-intel.h"
+
+/* Offset from regs */
+#define REVID 0x000
+#define REVID_SHIFT 16
+#define REVID_MASK GENMASK(31, 16)
+#define PADBAR 0x00c
+
+/* Offset from pad_regs */
+#define PADCFG0 0x000
+#define PADCFG0_RXEVCFG_SHIFT 25
+#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
+#define PADCFG0_RXEVCFG_LEVEL 0
+#define PADCFG0_RXEVCFG_EDGE 1
+#define PADCFG0_RXEVCFG_DISABLED 2
+#define PADCFG0_RXEVCFG_EDGE_BOTH 3
+#define PADCFG0_PREGFRXSEL BIT(24)
+#define PADCFG0_RXINV BIT(23)
+#define PADCFG0_GPIROUTIOXAPIC BIT(20)
+#define PADCFG0_GPIROUTSCI BIT(19)
+#define PADCFG0_GPIROUTSMI BIT(18)
+#define PADCFG0_GPIROUTNMI BIT(17)
+#define PADCFG0_PMODE_SHIFT 10
+#define PADCFG0_PMODE_MASK GENMASK(13, 10)
+#define PADCFG0_PMODE_GPIO 0
+#define PADCFG0_GPIORXDIS BIT(9)
+#define PADCFG0_GPIOTXDIS BIT(8)
+#define PADCFG0_GPIORXSTATE BIT(1)
+#define PADCFG0_GPIOTXSTATE BIT(0)
+
+#define PADCFG1 0x004
+#define PADCFG1_TERM_UP BIT(13)
+#define PADCFG1_TERM_SHIFT 10
+#define PADCFG1_TERM_MASK GENMASK(12, 10)
+#define PADCFG1_TERM_20K BIT(2)
+#define PADCFG1_TERM_5K BIT(1)
+#define PADCFG1_TERM_1K BIT(0)
+#define PADCFG1_TERM_833 (BIT(1) | BIT(0))
+
+#define PADCFG2 0x008
+#define PADCFG2_DEBEN BIT(0)
+#define PADCFG2_DEBOUNCE_SHIFT 1
+#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
+
+#define DEBOUNCE_PERIOD_NSEC 31250
+
+/* Additional features supported by the hardware */
+#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
+#define PINCTRL_FEATURE_1K_PD BIT(1)
+
+#define BOARD_UP_CHT01 0
+#define BOARD_UP_APL01 1
+#define BOARD_UP_UPCORE 2
+#define BOARD_UP_CORE_PLUS 3
+#define BOARD_AIOT_IP6801 4
+#define BOARD_UP_WHL01 5
+#define BOARD_UP_ISH 7
+#define BOARD_UPN_APL 8
+#define BOARD_UP_APL03 9
+#define BOARD_UPX_WHLite 10
+#define BOARD_UPX_TGL 11
+#define BOARD_UPX_EDGE_WHL2 12
+#define BOARD_UPN_EHL01 13
+#define BOARD_UPS_EHL01 14
+#define BOARD_UPX_ADLP01 15
+#define BOARD_UPN_ADLN01 16
+#define BOARD_UPS_ADLP01 15
+
+struct upboard_pin {
+ struct regmap_field *funcbit;
+ struct regmap_field *enbit;
+ struct regmap_field *dirbit;
+ /* native pin controllers: number, base, irq */
+ unsigned int gpio;
+ unsigned int base;
+ int irq;
+ void __iomem *regs;
+};
+
+struct upboard_pinctrl {
+ struct gpio_chip chip;
+ struct device *dev;
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_desc *pctldesc;
+ struct upboard_pin *pins;
+ struct regmap *regmap;
+ const unsigned int *rpi_mapping;
+ int ident;
+};
+
+enum upboard_func0_fpgabit {
+ UPFPGA_I2C0_EN = 8,
+ UPFPGA_I2C1_EN = 9,
+ UPFPGA_CEC0_EN = 12,
+ UPFPGA_ADC0_EN = 14,
+};
+
+static const struct reg_field upboard_i2c0_reg =
+ REG_FIELD(UPFPGA_REG_FUNC_EN0, UPFPGA_I2C0_EN, UPFPGA_I2C0_EN);
+
+static const struct reg_field upboard_i2c1_reg =
+ REG_FIELD(UPFPGA_REG_FUNC_EN0, UPFPGA_I2C1_EN, UPFPGA_I2C1_EN);
+
+static const struct reg_field upboard_adc0_reg =
+ REG_FIELD(UPFPGA_REG_FUNC_EN0, UPFPGA_ADC0_EN, UPFPGA_ADC0_EN);
+
+/* Pin group information */
+struct upboard_pingroup {
+ const char *name;
+ const unsigned int *pins;
+ size_t npins;
+};
+
+/* Pin function information */
+struct upboard_function {
+ const char *name;
+ const char * const *groups;
+ size_t ngroups;
+};
+
+#define UPBOARD_BIT_TO_PIN(r, bit) \
+ ((r) * UPFPGA_REGISTER_SIZE + (bit))
+
+/*
+ * UP board data
+ */
+
+#define UPBOARD_UP_BIT_TO_PIN(r, id) (UPBOARD_BIT_TO_PIN(r, UPFPGA_UP_##id))
+
+#define UPBOARD_UP_PIN_ANON(r, bit) \
+ { \
+ .number = UPBOARD_BIT_TO_PIN(r, bit), \
+ }
+
+#define UPBOARD_UP_PIN_NAME(r, id) \
+ { \
+ .number = UPBOARD_UP_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ }
+
+#define UPBOARD_UP_PIN_FUNC(r, id, data) \
+ { \
+ .number = UPBOARD_UP_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ .drv_data = (void *)(data), \
+ }
+
+#define UPBOARD_PIN_GROUP(n, p) \
+ { \
+ .name = (n), \
+ .pins = (p), \
+ .npins = ARRAY_SIZE((p)), \
+ }
+
+#define FUNCTION(n, g) \
+ { \
+ .name = (n), \
+ .groups = (g), \
+ .ngroups = ARRAY_SIZE((g)), \
+ }
+
+enum upboard_up_reg1_fpgabit {
+ UPFPGA_UP_I2C1_SDA,
+ UPFPGA_UP_I2C1_SCL,
+ UPFPGA_UP_ADC0,
+ UPFPGA_UP_GPIO17,
+ UPFPGA_UP_GPIO27,
+ UPFPGA_UP_GPIO22,
+ UPFPGA_UP_SPI_MOSI,
+ UPFPGA_UP_SPI_MISO,
+ UPFPGA_UP_SPI_CLK,
+ UPFPGA_UP_I2C0_SDA,
+ UPFPGA_UP_GPIO5,
+ UPFPGA_UP_GPIO6,
+ UPFPGA_UP_PWM1,
+ UPFPGA_UP_I2S_FRM,
+ UPFPGA_UP_GPIO26,
+ UPFPGA_UP_UART1_TX,
+};
+
+enum upboard_up_reg2_fpgabit {
+ UPFPGA_UP_UART1_RX,
+ UPFPGA_UP_I2S_CLK,
+ UPFPGA_UP_GPIO23,
+ UPFPGA_UP_GPIO24,
+ UPFPGA_UP_GPIO25,
+ UPFPGA_UP_SPI_CS0,
+ UPFPGA_UP_SPI_CS1,
+ UPFPGA_UP_I2C0_SCL,
+ UPFPGA_UP_PWM0,
+ UPFPGA_UP_GPIO16,
+ UPFPGA_UP_I2S_DIN,
+ UPFPGA_UP_I2S_DOUT,
+};
+
+#define UPFPGA_UP_UART1_RTS UPFPGA_UP_GPIO17
+#define UPFPGA_UP_UART1_CTS UPFPGA_UP_GPIO16
+
+static struct pinctrl_pin_desc upboard_up_pins[] = {
+ UPBOARD_UP_PIN_FUNC(0, I2C1_SDA, &upboard_i2c1_reg),
+ UPBOARD_UP_PIN_FUNC(0, I2C1_SCL, &upboard_i2c1_reg),
+ UPBOARD_UP_PIN_FUNC(0, ADC0, &upboard_adc0_reg),
+ UPBOARD_UP_PIN_NAME(0, UART1_RTS),
+ UPBOARD_UP_PIN_NAME(0, GPIO27),
+ UPBOARD_UP_PIN_NAME(0, GPIO22),
+ UPBOARD_UP_PIN_NAME(0, SPI_MOSI),
+ UPBOARD_UP_PIN_NAME(0, SPI_MISO),
+ UPBOARD_UP_PIN_NAME(0, SPI_CLK),
+ UPBOARD_UP_PIN_FUNC(0, I2C0_SDA, &upboard_i2c0_reg),
+ UPBOARD_UP_PIN_NAME(0, GPIO5),
+ UPBOARD_UP_PIN_NAME(0, GPIO6),
+ UPBOARD_UP_PIN_NAME(0, PWM1),
+ UPBOARD_UP_PIN_NAME(0, I2S_FRM),
+ UPBOARD_UP_PIN_NAME(0, GPIO26),
+ UPBOARD_UP_PIN_NAME(0, UART1_TX),
+ /* register 1 */
+ UPBOARD_UP_PIN_NAME(1, UART1_RX),
+ UPBOARD_UP_PIN_NAME(1, I2S_CLK),
+ UPBOARD_UP_PIN_NAME(1, GPIO23),
+ UPBOARD_UP_PIN_NAME(1, GPIO24),
+ UPBOARD_UP_PIN_NAME(1, GPIO25),
+ UPBOARD_UP_PIN_NAME(1, SPI_CS0),
+ UPBOARD_UP_PIN_NAME(1, SPI_CS1),
+ UPBOARD_UP_PIN_FUNC(1, I2C0_SCL, &upboard_i2c0_reg),
+ UPBOARD_UP_PIN_NAME(1, PWM0),
+ UPBOARD_UP_PIN_NAME(1, UART1_CTS),
+ UPBOARD_UP_PIN_NAME(1, I2S_DIN),
+ UPBOARD_UP_PIN_NAME(1, I2S_DOUT),
+};
+
+static const unsigned int upboard_up_rpi_mapping[] = {
+ UPBOARD_UP_BIT_TO_PIN(0, I2C0_SDA),
+ UPBOARD_UP_BIT_TO_PIN(1, I2C0_SCL),
+ UPBOARD_UP_BIT_TO_PIN(0, I2C1_SDA),
+ UPBOARD_UP_BIT_TO_PIN(0, I2C1_SCL),
+ UPBOARD_UP_BIT_TO_PIN(0, ADC0),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO5),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO6),
+ UPBOARD_UP_BIT_TO_PIN(1, SPI_CS1),
+ UPBOARD_UP_BIT_TO_PIN(1, SPI_CS0),
+ UPBOARD_UP_BIT_TO_PIN(0, SPI_MISO),
+ UPBOARD_UP_BIT_TO_PIN(0, SPI_MOSI),
+ UPBOARD_UP_BIT_TO_PIN(0, SPI_CLK),
+ UPBOARD_UP_BIT_TO_PIN(1, PWM0),
+ UPBOARD_UP_BIT_TO_PIN(0, PWM1),
+ UPBOARD_UP_BIT_TO_PIN(0, UART1_TX),
+ UPBOARD_UP_BIT_TO_PIN(1, UART1_RX),
+ UPBOARD_UP_BIT_TO_PIN(1, GPIO16),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO17),
+ UPBOARD_UP_BIT_TO_PIN(1, I2S_CLK),
+ UPBOARD_UP_BIT_TO_PIN(0, I2S_FRM),
+ UPBOARD_UP_BIT_TO_PIN(1, I2S_DIN),
+ UPBOARD_UP_BIT_TO_PIN(1, I2S_DOUT),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO22),
+ UPBOARD_UP_BIT_TO_PIN(1, GPIO23),
+ UPBOARD_UP_BIT_TO_PIN(1, GPIO24),
+ UPBOARD_UP_BIT_TO_PIN(1, GPIO25),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO26),
+ UPBOARD_UP_BIT_TO_PIN(0, GPIO27),
+};
+
+static const unsigned int uart1_pins[] = { 14, 15, 16, 17 };
+static const unsigned int uart2_pins[] = { 25, 27 };
+static const unsigned int i2c0_pins[] = { 0, 1 };
+static const unsigned int i2c1_pins[] = { 2, 3 };
+static const unsigned int spi2_pins[] = { 8, 9, 10, 11 };
+static const unsigned int i2s0_pins[] = { 18, 19, 20, 21 };
+static const unsigned int pwm0_pins[] = { 12 };
+static const unsigned int pwm1_pins[] = { 13 };
+static const unsigned int adc0_pins[] = { 4 };
+
+static const struct upboard_pingroup pin_groups[] = {
+ UPBOARD_PIN_GROUP("uart1_grp", uart1_pins),
+ UPBOARD_PIN_GROUP("uart2_grp", uart2_pins),
+ UPBOARD_PIN_GROUP("i2c0_grp", i2c0_pins),
+ UPBOARD_PIN_GROUP("i2c1_grp", i2c1_pins),
+ UPBOARD_PIN_GROUP("spi2_grp", spi2_pins),
+ UPBOARD_PIN_GROUP("i2s0_grp", i2s0_pins),
+ UPBOARD_PIN_GROUP("pwm0_grp", pwm0_pins),
+ UPBOARD_PIN_GROUP("pwm1_grp", pwm1_pins),
+ UPBOARD_PIN_GROUP("adc0_grp", adc0_pins),
+};
+
+static const char * const uart1_groups[] = { "uart1_grp" };
+static const char * const uart2_groups[] = { "uart2_grp" };
+static const char * const i2c0_groups[] = { "i2c0_grp" };
+static const char * const i2c1_groups[] = { "i2c1_grp" };
+static const char * const spi2_groups[] = { "spi2_grp" };
+static const char * const i2s0_groups[] = { "i2s0_grp" };
+static const char * const pwm0_groups[] = { "pwm0_grp" };
+static const char * const pwm1_groups[] = { "pwm1_grp" };
+static const char * const adc0_groups[] = { "adc0_grp" };
+
+static const struct upboard_function pin_functions[] = {
+ FUNCTION("uart1", uart1_groups),
+ FUNCTION("uart2", uart2_groups),
+ FUNCTION("i2c0", i2c0_groups),
+ FUNCTION("i2c1", i2c1_groups),
+ FUNCTION("spi2", spi2_groups),
+ FUNCTION("i2s0", i2s0_groups),
+ FUNCTION("pwm0", pwm0_groups),
+ FUNCTION("pwm1", pwm1_groups),
+ FUNCTION("adc0", adc0_groups),
+};
+
+/*
+ * UP^2 board data
+ */
+
+#define UPBOARD_UP2_BIT_TO_PIN(r, id) (UPBOARD_BIT_TO_PIN(r, UPFPGA_UP2_##id))
+
+#define UPBOARD_UP2_PIN_ANON(r, bit) \
+ { \
+ .number = UPBOARD_BIT_TO_PIN(r, bit), \
+ .name = "NONAME", \
+ }
+
+#define UPBOARD_UP2_PIN_NAME(r, id) \
+ { \
+ .number = UPBOARD_UP2_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ }
+
+#define UPBOARD_UP2_PIN_FUNC(r, id, data) \
+ { \
+ .number = UPBOARD_UP2_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ .drv_data = (void *)(data), \
+ }
+
+enum upboard_up2_reg0_fpgabit {
+ UPFPGA_UP2_UART1_TXD,
+ UPFPGA_UP2_UART1_RXD,
+ UPFPGA_UP2_UART1_RTS,
+ UPFPGA_UP2_UART1_CTS,
+ UPFPGA_UP2_GPIO3,
+ UPFPGA_UP2_GPIO5,
+ UPFPGA_UP2_GPIO6,
+ UPFPGA_UP2_GPIO11,
+ UPFPGA_UP2_EXHAT_LVDS1n,
+ UPFPGA_UP2_EXHAT_LVDS1p,
+ UPFPGA_UP2_SPI2_TXD,
+ UPFPGA_UP2_SPI2_RXD,
+ UPFPGA_UP2_SPI2_FS1,
+ UPFPGA_UP2_SPI2_FS0,
+ UPFPGA_UP2_SPI2_CLK,
+ UPFPGA_UP2_SPI1_TXD,
+};
+
+enum upboard_up2_reg1_fpgabit {
+ UPFPGA_UP2_SPI1_RXD,
+ UPFPGA_UP2_SPI1_FS1,
+ UPFPGA_UP2_SPI1_FS0,
+ UPFPGA_UP2_SPI1_CLK,
+ UPFPGA_UP2_BIT20,
+ UPFPGA_UP2_BIT21,
+ UPFPGA_UP2_BIT22,
+ UPFPGA_UP2_BIT23,
+ UPFPGA_UP2_PWM1,
+ UPFPGA_UP2_PWM0,
+ UPFPGA_UP2_EXHAT_LVDS0n,
+ UPFPGA_UP2_EXHAT_LVDS0p,
+ UPFPGA_UP2_I2C0_SCL,
+ UPFPGA_UP2_I2C0_SDA,
+ UPFPGA_UP2_I2C1_SCL,
+ UPFPGA_UP2_I2C1_SDA,
+};
+
+enum upboard_up2_reg2_fpgabit {
+ UPFPGA_UP2_EXHAT_LVDS3n,
+ UPFPGA_UP2_EXHAT_LVDS3p,
+ UPFPGA_UP2_EXHAT_LVDS4n,
+ UPFPGA_UP2_EXHAT_LVDS4p,
+ UPFPGA_UP2_EXHAT_LVDS5n,
+ UPFPGA_UP2_EXHAT_LVDS5p,
+ UPFPGA_UP2_I2S_SDO,
+ UPFPGA_UP2_I2S_SDI,
+ UPFPGA_UP2_I2S_WS_SYNC,
+ UPFPGA_UP2_I2S_BCLK,
+ UPFPGA_UP2_EXHAT_LVDS6n,
+ UPFPGA_UP2_EXHAT_LVDS6p,
+ UPFPGA_UP2_EXHAT_LVDS7n,
+ UPFPGA_UP2_EXHAT_LVDS7p,
+ UPFPGA_UP2_EXHAT_LVDS2n,
+ UPFPGA_UP2_EXHAT_LVDS2p,
+};
+
+static struct pinctrl_pin_desc upboard_up2_pins[] = {
+ UPBOARD_UP2_PIN_NAME(0, UART1_TXD),
+ UPBOARD_UP2_PIN_NAME(0, UART1_RXD),
+ UPBOARD_UP2_PIN_NAME(0, UART1_RTS),
+ UPBOARD_UP2_PIN_NAME(0, UART1_CTS),
+ UPBOARD_UP2_PIN_NAME(0, GPIO3),
+ UPBOARD_UP2_PIN_NAME(0, GPIO5),
+ UPBOARD_UP2_PIN_NAME(0, GPIO6),
+ UPBOARD_UP2_PIN_NAME(0, GPIO11),
+ UPBOARD_UP2_PIN_NAME(0, EXHAT_LVDS1n),
+ UPBOARD_UP2_PIN_NAME(0, EXHAT_LVDS1p),
+ UPBOARD_UP2_PIN_NAME(0, SPI2_TXD),
+ UPBOARD_UP2_PIN_NAME(0, SPI2_RXD),
+ UPBOARD_UP2_PIN_NAME(0, SPI2_FS1),
+ UPBOARD_UP2_PIN_NAME(0, SPI2_FS0),
+ UPBOARD_UP2_PIN_NAME(0, SPI2_CLK),
+ UPBOARD_UP2_PIN_NAME(0, SPI1_TXD),
+ UPBOARD_UP2_PIN_NAME(1, SPI1_RXD),
+ UPBOARD_UP2_PIN_NAME(1, SPI1_FS1),
+ UPBOARD_UP2_PIN_NAME(1, SPI1_FS0),
+ UPBOARD_UP2_PIN_NAME(1, SPI1_CLK),
+ UPBOARD_UP2_PIN_ANON(1, 4),
+ UPBOARD_UP2_PIN_ANON(1, 5),
+ UPBOARD_UP2_PIN_ANON(1, 6),
+ UPBOARD_UP2_PIN_ANON(1, 7),
+ UPBOARD_UP2_PIN_NAME(1, PWM1),
+ UPBOARD_UP2_PIN_NAME(1, PWM0),
+ UPBOARD_UP2_PIN_NAME(1, EXHAT_LVDS0n),
+ UPBOARD_UP2_PIN_NAME(1, EXHAT_LVDS0p),
+ UPBOARD_UP2_PIN_FUNC(1, I2C0_SCL, &upboard_i2c0_reg),
+ UPBOARD_UP2_PIN_FUNC(1, I2C0_SDA, &upboard_i2c0_reg),
+ UPBOARD_UP2_PIN_FUNC(1, I2C1_SCL, &upboard_i2c1_reg),
+ UPBOARD_UP2_PIN_FUNC(1, I2C1_SDA, &upboard_i2c1_reg),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS3n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS3p),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS4n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS4p),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS5n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS5p),
+ UPBOARD_UP2_PIN_NAME(2, I2S_SDO),
+ UPBOARD_UP2_PIN_NAME(2, I2S_SDI),
+ UPBOARD_UP2_PIN_NAME(2, I2S_WS_SYNC),
+ UPBOARD_UP2_PIN_NAME(2, I2S_BCLK),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS6n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS6p),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS7n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS7p),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS2n),
+ UPBOARD_UP2_PIN_NAME(2, EXHAT_LVDS2p),
+};
+
+static const unsigned int upboard_up2_rpi_mapping[] = {
+ UPBOARD_UP2_BIT_TO_PIN(1, I2C0_SDA),
+ UPBOARD_UP2_BIT_TO_PIN(1, I2C0_SCL),
+ UPBOARD_UP2_BIT_TO_PIN(1, I2C1_SDA),
+ UPBOARD_UP2_BIT_TO_PIN(1, I2C1_SCL),
+ UPBOARD_UP2_BIT_TO_PIN(0, GPIO3),
+ UPBOARD_UP2_BIT_TO_PIN(0, GPIO11),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI2_CLK),
+ UPBOARD_UP2_BIT_TO_PIN(1, SPI1_FS1),
+ UPBOARD_UP2_BIT_TO_PIN(1, SPI1_FS0),
+ UPBOARD_UP2_BIT_TO_PIN(1, SPI1_RXD),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI1_TXD),
+ UPBOARD_UP2_BIT_TO_PIN(1, SPI1_CLK),
+ UPBOARD_UP2_BIT_TO_PIN(1, PWM0),
+ UPBOARD_UP2_BIT_TO_PIN(1, PWM1),
+ UPBOARD_UP2_BIT_TO_PIN(0, UART1_TXD),
+ UPBOARD_UP2_BIT_TO_PIN(0, UART1_RXD),
+ UPBOARD_UP2_BIT_TO_PIN(0, UART1_CTS),
+ UPBOARD_UP2_BIT_TO_PIN(0, UART1_RTS),
+ UPBOARD_UP2_BIT_TO_PIN(2, I2S_BCLK),
+ UPBOARD_UP2_BIT_TO_PIN(2, I2S_WS_SYNC),
+ UPBOARD_UP2_BIT_TO_PIN(2, I2S_SDI),
+ UPBOARD_UP2_BIT_TO_PIN(2, I2S_SDO),
+ UPBOARD_UP2_BIT_TO_PIN(0, GPIO6),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI2_FS1),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI2_RXD),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI2_TXD),
+ UPBOARD_UP2_BIT_TO_PIN(0, SPI2_FS0),
+ UPBOARD_UP2_BIT_TO_PIN(0, GPIO5),
+};
+
+/*
+ * UP Core board + CREX carrier board data
+ */
+
+#define UPBOARD_UPCORE_CREX_BIT_TO_PIN(r, id) \
+ (UPBOARD_BIT_TO_PIN(r, UPFPGA_UPCORE_CREX_##id))
+
+#define UPBOARD_UPCORE_CREX_PIN_ANON(r, bit) \
+ { \
+ .number = UPBOARD_BIT_TO_PIN(r, bit), \
+ }
+
+#define UPBOARD_UPCORE_CREX_PIN_NAME(r, id) \
+ { \
+ .number = UPBOARD_UPCORE_CREX_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ }
+
+#define UPBOARD_UPCORE_CREX_PIN_FUNC(r, id, data) \
+ { \
+ .number = UPBOARD_UPCORE_CREX_BIT_TO_PIN(r, id), \
+ .name = #id, \
+ .drv_data = (void *)(data), \
+ }
+
+enum upboard_upcore_crex_reg1_fpgabit {
+ UPFPGA_UPCORE_CREX_I2C0_SDA,
+ UPFPGA_UPCORE_CREX_I2C0_SCL,
+ UPFPGA_UPCORE_CREX_I2C1_SDA,
+ UPFPGA_UPCORE_CREX_I2C1_SCL,
+ UPFPGA_UPCORE_CREX_SPI2_CS0,
+ UPFPGA_UPCORE_CREX_SPI2_CS1,
+ UPFPGA_UPCORE_CREX_SPI2_MOSI,
+ UPFPGA_UPCORE_CREX_SPI2_MISO,
+ UPFPGA_UPCORE_CREX_SPI2_CLK,
+ UPFPGA_UPCORE_CREX_UART1_TXD,
+ UPFPGA_UPCORE_CREX_UART1_RXD,
+ UPFPGA_UPCORE_CREX_PWM0,
+ UPFPGA_UPCORE_CREX_PWM1,
+ UPFPGA_UPCORE_CREX_I2S2_FRM,
+ UPFPGA_UPCORE_CREX_I2S2_CLK,
+ UPFPGA_UPCORE_CREX_I2S2_RX,
+};
+
+enum upboard_upcore_crex_reg2_fpgabit {
+ UPFPGA_UPCORE_CREX_I2S2_TX,
+ UPFPGA_UPCORE_CREX_GPIO0,
+ UPFPGA_UPCORE_CREX_GPIO2,
+ UPFPGA_UPCORE_CREX_GPIO3,
+ UPFPGA_UPCORE_CREX_GPIO4,
+ UPFPGA_UPCORE_CREX_GPIO9,
+};
+
+static struct pinctrl_pin_desc upboard_upcore_crex_pins[] = {
+ UPBOARD_UPCORE_CREX_PIN_FUNC(0, I2C0_SDA, &upboard_i2c0_reg),
+ UPBOARD_UPCORE_CREX_PIN_FUNC(0, I2C0_SCL, &upboard_i2c0_reg),
+ UPBOARD_UPCORE_CREX_PIN_FUNC(0, I2C1_SDA, &upboard_i2c1_reg),
+ UPBOARD_UPCORE_CREX_PIN_FUNC(0, I2C1_SCL, &upboard_i2c1_reg),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, SPI2_CS0),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, SPI2_CS1),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, SPI2_MOSI),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, SPI2_MISO),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, SPI2_CLK),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, UART1_TXD),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, UART1_RXD),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, PWM0),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, PWM1),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, I2S2_FRM),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, I2S2_CLK),
+ UPBOARD_UPCORE_CREX_PIN_NAME(0, I2S2_RX),
+ /* register 1 */
+ UPBOARD_UPCORE_CREX_PIN_NAME(1, I2S2_TX),
+ UPBOARD_UPCORE_CREX_PIN_NAME(1, GPIO0),
+ UPBOARD_UPCORE_CREX_PIN_FUNC(1, GPIO2, &upboard_adc0_reg),
+ UPBOARD_UPCORE_CREX_PIN_NAME(1, GPIO3),
+ UPBOARD_UPCORE_CREX_PIN_NAME(1, GPIO4),
+ UPBOARD_UPCORE_CREX_PIN_NAME(1, GPIO9),
+};
+
+static unsigned int upboard_upcore_crex_rpi_mapping[] = {
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2C0_SDA),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2C0_SCL),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2C1_SDA),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2C1_SCL),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, GPIO0),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, GPIO2),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, GPIO3),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, SPI2_CS1),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, SPI2_CS0),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, SPI2_MISO),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, SPI2_MOSI),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, SPI2_CLK),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, PWM0),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, PWM1),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, UART1_TXD),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, UART1_RXD),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, GPIO9),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, GPIO4),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2S2_CLK),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2S2_FRM),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(0, I2S2_RX),
+ UPBOARD_UPCORE_CREX_BIT_TO_PIN(1, I2S2_TX),
+};
+
+/*
+ * UP Core board + CRST02 carrier board data
+ */
+
+#define upboard_upcore_crst02_pins upboard_upcore_crex_pins
+#define upboard_upcore_crst02_rpi_mapping upboard_upcore_crex_rpi_mapping
+
+static int upboard_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
+ unsigned int group)
+{
+ return 0;
+}
+
+static int upboard_fpga_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ const struct pin_desc * const pd = pin_desc_get(pctldev, pin);
+ const struct upboard_pin *p;
+ int ret;
+
+ p = pd->drv_data;
+ if (p->funcbit) {
+ ret = regmap_field_write(p->funcbit, 0);
+ if (ret)
+ return ret;
+ }
+
+ if (p->enbit) {
+ ret = regmap_field_write(p->enbit, 1);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int upboard_fpga_request_free(struct pinctrl_dev *pctldev,
+ unsigned int pin)
+{
+ const struct pin_desc * const pd = pin_desc_get(pctldev, pin);
+ const struct upboard_pin *p;
+ int ret;
+
+ p = pd->drv_data;
+ if (p->funcbit) {
+ ret = regmap_field_write(p->funcbit, 1);
+ if (ret)
+ return ret;
+ }
+
+ if (p->enbit) {
+ ret = regmap_field_write(p->enbit, 0);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int upboard_fpga_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ const struct pin_desc * const pd = pin_desc_get(pctldev, pin);
+ const struct upboard_pin *p;
+
+ p = pd->drv_data;
+ upboard_fpga_request_enable(pctldev, range, pin);
+
+ return regmap_field_write(p->dirbit, input);
+}
+
+static int upboard_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ return 0;
+}
+
+static const char *upboard_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return NULL;
+}
+
+static int upboard_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned int *num_groups)
+{
+ *groups = NULL;
+ *num_groups = 0;
+ return 0;
+}
+
+static const struct pinmux_ops upboard_pinmux_ops = {
+ .get_functions_count = upboard_get_functions_count,
+ .get_function_groups = upboard_get_function_groups,
+ .get_function_name = upboard_get_function_name,
+ .set_mux = upboard_set_mux,
+ .gpio_request_enable = upboard_fpga_request_enable,
+ .gpio_set_direction = upboard_fpga_set_direction,
+};
+
+static int upboard_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ return 0;
+}
+
+static const char *upboard_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return NULL;
+}
+
+static const struct pinctrl_ops upboard_pinctrl_ops = {
+ .get_groups_count = upboard_get_groups_count,
+ .get_group_name = upboard_get_group_name,
+};
+
+static struct pinctrl_desc upboard_up_pinctrl_desc = {
+ .pins = upboard_up_pins,
+ .npins = ARRAY_SIZE(upboard_up_pins),
+ .pctlops = &upboard_pinctrl_ops,
+ .pmxops = &upboard_pinmux_ops,
+ .owner = THIS_MODULE,
+};
+
+static struct pinctrl_desc upboard_up2_pinctrl_desc = {
+ .pins = upboard_up2_pins,
+ .npins = ARRAY_SIZE(upboard_up2_pins),
+ .pctlops = &upboard_pinctrl_ops,
+ .pmxops = &upboard_pinmux_ops,
+ .owner = THIS_MODULE,
+};
+
+static struct pinctrl_desc upboard_upcore_crex_pinctrl_desc = {
+ .pins = upboard_upcore_crex_pins,
+ .npins = ARRAY_SIZE(upboard_upcore_crex_pins),
+ .pctlops = &upboard_pinctrl_ops,
+ .pmxops = &upboard_pinmux_ops,
+ .owner = THIS_MODULE,
+};
+
+static struct pinctrl_desc upboard_upcore_crst02_pinctrl_desc = {
+ .pins = upboard_upcore_crst02_pins,
+ .npins = ARRAY_SIZE(upboard_upcore_crst02_pins),
+ .pctlops = &upboard_pinctrl_ops,
+ .pmxops = &upboard_pinmux_ops,
+ .owner = THIS_MODULE,
+};
+
+static void upboard_alt_func_enable(struct gpio_chip *gc, const char *name, int id)
+{
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ int offset[pctrl->pctldesc->npins];
+ int i, cnt;
+
+ /* find all pins */
+ for (i = 0, cnt = 0; i < pctrl->pctldesc->npins; i++) {
+ if (strstr(pctrl->pctldesc->pins[i].name, name))
+ offset[cnt++] = i;
+ }
+
+ for (i = 0; i < cnt; i++) {
+ if (pinctrl_gpio_request(pctrl->pins[offset[i]].gpio))
+ return; /* this pin is being used */
+
+ pinctrl_gpio_free(pctrl->pins[offset[i]].gpio);
+ }
+
+ /* change to alternate function */
+ for (i = 0; i < cnt; i++) {
+ if (pctrl->pins[offset[i]].regs == NULL)
+ continue;
+ bool input = false;
+ int mode = 1; /* default */
+ unsigned int val = readl(pctrl->pins[offset[i]].regs);
+
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "I2C")) {
+ switch (id) {
+ case BOARD_UPN_ADLN01:
+ case BOARD_UPX_ADLP01:
+ mode = 2;
+ break;
+ default:
+ break;
+ }
+ val |= mode<<PADCFG0_PMODE_SHIFT;
+ writel(val, pctrl->pins[offset[i]].regs);
+ upboard_fpga_request_free(pctrl->pctldev, offset[i]);
+ continue;
+ } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "UART")) {
+ switch (id) {
+ case BOARD_UPN_EHL01:
+ case BOARD_UPS_EHL01:
+ mode = 4;
+ break;
+ case BOARD_UPN_ADLN01:
+ case BOARD_UPX_ADLP01:
+ mode = 2;
+ break;
+ default:
+ break;
+ }
+ } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "SPI")) {
+ switch (id) {
+ case BOARD_UP_WHL01:
+ mode = 3;
+ break;
+ case BOARD_UPN_ADLN01:
+ case BOARD_UPX_ADLP01:
+ mode = 7;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MOSI")) {
+ val &= ~PADCFG0_GPIOTXDIS;
+ val |= PADCFG0_GPIORXDIS;
+ }
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MISO")) {
+ val |= PADCFG0_GPIORXDIS;
+ }
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CLK")) {
+ val &= ~PADCFG0_GPIOTXDIS;
+ val |= PADCFG0_GPIORXDIS;
+ }
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CS0")) {
+ val |= PADCFG0_GPIORXDIS;
+ }
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CS1")) {
+ continue;
+ }
+ break;
+ default:
+ break;
+ }
+ } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "I2S")) {
+ switch (id) {
+ case BOARD_UPX_ADLP01:
+ mode = 4;
+ break;
+ default:
+ break;
+ }
+ }
+ val |= mode<<PADCFG0_PMODE_SHIFT;
+ writel(val, pctrl->pins[offset[i]].regs);
+
+ /* input pins */
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "RX"))
+ input = true;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CTS"))
+ input = true;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "ADC"))
+ input = true;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MISO"))
+ input = true;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "DIN"))
+ input = true;
+ if (strstr(pctrl->pctldesc->pins[offset[i]].name, "SDI"))
+ input = true;
+ upboard_fpga_set_direction(pctrl->pctldev, NULL, offset[i], input);
+ }
+}
+
+static int upboard_rpi_to_native_gpio(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ unsigned int pin = pctrl->rpi_mapping[gpio];
+ struct pinctrl_gpio_range *range;
+
+ range = pinctrl_find_gpio_range_from_pin(pctrl->pctldev, pin);
+ if (!range)
+ return -ENODEV;
+
+ return range->base;
+}
+
+static int upboard_gpio_request(struct gpio_chip *gc, unsigned int offset)
+{
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+
+ return pinctrl_gpio_request(gpio);
+}
+
+static void upboard_gpio_free(struct gpio_chip *gc, unsigned int offset)
+{
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+ unsigned int pin = pctrl->rpi_mapping[offset];
+ char name[strlen(pctrl->pctldesc->pins[pin].name)];
+ char *p;
+
+ pinctrl_gpio_free(gpio);
+
+ strcpy(name, pctrl->pctldesc->pins[pin].name);
+ p = name;
+ upboard_alt_func_enable(gc, strsep(&p, "_"), pctrl->ident);
+}
+
+static int upboard_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+
+ return gpiod_get_value(gpio_to_desc(gpio));
+}
+
+static void upboard_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ unsigned int pin = pctrl->rpi_mapping[offset];
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+
+ gpiod_set_value(gpio_to_desc(gpio), value);
+
+ /* APL03 board open drain GPIO */
+ if (pctrl->ident == BOARD_UP_APL03) {
+ if (pin == 0 || pin == 1) {
+ int val = readl(pctrl->pins[pin].regs);
+
+ if (value)
+ val |= PADCFG0_GPIOTXDIS;
+ else
+ val &= ~PADCFG0_GPIOTXDIS;
+
+ writel(val, pctrl->pins[pin].regs);
+ }
+ }
+}
+
+static int upboard_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ unsigned int pin = pctrl->rpi_mapping[offset];
+ struct pinctrl_gpio_range *range;
+
+ range = pinctrl_find_gpio_range_from_pin(pctrl->pctldev, pin);
+ upboard_fpga_set_direction(pctrl->pctldev, range, pin, true);
+
+ return gpiod_direction_input(gpio_to_desc(gpio));
+}
+
+static int upboard_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ int gpio = upboard_rpi_to_native_gpio(gc, offset);
+ struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
+ unsigned int pin = pctrl->rpi_mapping[offset];
+ struct pinctrl_gpio_range *range;
+
+ range = pinctrl_find_gpio_range_from_pin(pctrl->pctldev, pin);
+ upboard_fpga_set_direction(pctrl->pctldev, range, pin, false);
+
+ return gpiod_direction_output(gpio_to_desc(gpio), value);
+}
+
+static void __iomem *upboard_get_regs(struct gpio_chip *gc, unsigned int gpio, unsigned int reg)
+{
+ struct platform_device *pdev = to_platform_device(gc->parent);
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
+ size_t nregs;
+ void __iomem *base = NULL;
+ u32 offset, value;
+ int pin = gpio-gc->base;
+
+ /* check Intel pin controller for all platform */
+ if (pctrl->ncommunities > 1) {
+ int i, j, offset = 0;
+
+ pin = -1;
+ for (i = 0; i < pctrl->ncommunities; i++) {
+ struct intel_community *community = &pctrl->communities[i];
+
+ for (j = 0; j < community->ngpps ; j++) {
+ struct intel_padgroup gpps = community->gpps[j];
+
+ if (gpio < gc->base + gpps.gpio_base + gpps.size) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM,
+ community->barno);
+ pin = gpio-gc->base-gpps.gpio_base +
+ offset-community->pin_base;
+ break;
+ }
+
+ offset += gpps.size;
+ }
+
+ if (pin != -1)
+ break;
+ }
+ }
+
+ base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (base == NULL)
+ return base;
+
+ offset = readl(base + PADBAR);
+ value = readl(base + REVID);
+
+ if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94)
+ nregs = 4;
+ else
+ nregs = 2;
+
+ return base + offset + reg + pin * nregs * 4;
+}
+
+int upboard_acpi_node_pin_mapping(struct upboard_fpga *fpga,
+ struct upboard_pinctrl *pctrl,
+ const char *propname,
+ const char *pinctl_name,
+ unsigned int pin_offset)
+{
+ struct gpio_descs *descs;
+ int ret, i;
+
+ descs = devm_gpiod_get_array(fpga->dev, propname, GPIOD_ASIS);
+ if (IS_ERR(descs)) {
+ ret = PTR_ERR(descs);
+ if (ret != -EPROBE_DEFER)
+ dev_err(fpga->dev, "Failed to get %s gpios", propname);
+
+ return ret;
+ }
+
+ for (i = 0; i < descs->ndescs; i++) {
+ struct gpio_desc *desc = descs->desc[i];
+ struct gpio_chip *gc = gpiod_to_chip(desc);
+
+ pctrl->pins[i].gpio = desc_to_gpio(desc);
+ pctrl->pins[i].base = gc->base;
+ pctrl->pins[i].irq = gpiod_to_irq(desc);
+ pctrl->pins[i].regs =
+ upboard_get_regs(gc,
+ desc_to_gpio(desc) - gc->base,
+ PADCFG0);
+
+ /* The GPIOs may not be contiguous, so add them 1-by-1 */
+ ret = gpiochip_add_pin_range(gpiod_to_chip(desc), pinctl_name,
+ desc_to_gpio(desc) - gc->base,
+ pin_offset + i, 1);
+ if (ret)
+ return ret;
+ }
+
+ /* dispose acpi resource */
+ devm_gpiod_put_array(fpga->dev, descs);
+
+ return ret;
+}
+
+static struct gpio_chip upboard_gpio_chip = {
+ .label = "Raspberry Pi compatible UP GPIO",
+ .base = 0,
+ .request = upboard_gpio_request,
+ .free = upboard_gpio_free,
+ .get = upboard_gpio_get,
+ .set = upboard_gpio_set,
+ .direction_input = upboard_gpio_direction_input,
+ .direction_output = upboard_gpio_direction_output,
+ .owner = THIS_MODULE,
+};
+
+/* DMI Matches for older bios without fpga initialization */
+static const struct dmi_system_id upboard_dmi_table[] __initconst = {
+ {
+ .ident = BOARD_UP_APL03,
+ .matches = { /* UP 4000 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UP-APL03"),
+ },
+ },
+ {
+ .ident = BOARD_UP_WHL01,
+ .matches = { /* UPX WHL */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UP-WHL01"),
+ },
+ },
+ {
+ .ident = BOARD_UPX_TGL,
+ .matches = { /* UP i11 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-TGL01"),
+ },
+ },
+ {
+ .ident = BOARD_UPN_EHL01,
+ .matches = { /* UP 6000 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPN-EHL01"),
+ },
+ },
+ {
+ .ident = BOARD_UPS_EHL01,
+ .matches = { /* UP squared v2 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPS-EHL01"),
+ },
+ },
+ {
+ .ident = BOARD_UPX_ADLP01,
+ .matches = { /* UP Xtreme i12 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPX-ADLP01"),
+ },
+ },
+ {
+ .ident = BOARD_UPN_ADLN01,
+ .matches = { /* UP 7000 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPN-ADLN01"),
+ },
+ },
+ {
+ .ident = BOARD_UPS_ADLP01,
+ .matches = { /* UP Squared i12 */
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "AAEON"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "UPS-ADLP01"),
+ },
+ },
+ { } /* Terminating entry */
+};
+
+static int __init upboard_pinctrl_probe(struct platform_device *pdev)
+{
+ struct upboard_fpga * const fpga = dev_get_drvdata(pdev->dev.parent);
+ struct acpi_device * const adev = ACPI_COMPANION(&pdev->dev);
+ struct pinctrl_desc *pctldesc;
+ struct upboard_pinctrl *pctrl;
+ struct upboard_pin *pins;
+ const struct dmi_system_id *system_id;
+ const char *hid;
+ const unsigned int *rpi_mapping;
+ unsigned int ngpio;
+ int ret;
+ int i;
+
+ if (!fpga)
+ return -EINVAL;
+
+ if (!adev)
+ return -ENODEV;
+
+ /* set pin desc and rpi GPIO mapping table by HID */
+ hid = acpi_device_hid(adev);
+ if (!strcmp(hid, "AANT0F00") || !strcmp(hid, "AANT0F04") ||
+ !strcmp(hid, "AANT0000")) {
+ pctldesc = &upboard_up_pinctrl_desc;
+ rpi_mapping = upboard_up_rpi_mapping;
+ ngpio = ARRAY_SIZE(upboard_up_rpi_mapping);
+ } else if (!strcmp(hid, "AANT0F01")) {
+ pctldesc = &upboard_up2_pinctrl_desc;
+ rpi_mapping = upboard_up2_rpi_mapping;
+ ngpio = ARRAY_SIZE(upboard_up2_rpi_mapping);
+ } else if (!strcmp(hid, "AANT0F02")) {
+ pctldesc = &upboard_upcore_crex_pinctrl_desc;
+ rpi_mapping = upboard_upcore_crex_rpi_mapping;
+ ngpio = ARRAY_SIZE(upboard_upcore_crex_rpi_mapping);
+ } else if (!strcmp(hid, "AANT0F03")) {
+ pctldesc = &upboard_upcore_crst02_pinctrl_desc;
+ rpi_mapping = upboard_upcore_crst02_rpi_mapping;
+ ngpio = ARRAY_SIZE(upboard_upcore_crst02_rpi_mapping);
+ } else
+ return -ENODEV;
+
+ pctldesc->name = dev_name(&pdev->dev);
+
+ pins = devm_kcalloc(&pdev->dev, pctldesc->npins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ /* initialise pins */
+ for (i = 0; i < pctldesc->npins; i++) {
+ struct upboard_pin *pin = &pins[i];
+ struct pinctrl_pin_desc *pd = (struct pinctrl_pin_desc *) &pctldesc->pins[i];
+ struct reg_field fldconf = {0};
+ unsigned int regoff = (pd->number / UPFPGA_REGISTER_SIZE);
+ unsigned int lsb = pd->number % UPFPGA_REGISTER_SIZE;
+
+ pin->funcbit = NULL;
+
+ if (pd->drv_data) {
+ fldconf = *(struct reg_field *)pd->drv_data;
+
+ pin->funcbit = devm_regmap_field_alloc(&pdev->dev,
+ fpga->regmap,
+ fldconf);
+ if (IS_ERR(pin->funcbit))
+ return PTR_ERR(pin->funcbit);
+ }
+
+ pin->enbit = NULL;
+ fldconf.reg = UPFPGA_REG_GPIO_EN0 + regoff;
+ fldconf.lsb = lsb;
+ fldconf.msb = lsb;
+
+ pin->enbit = devm_regmap_field_alloc(&pdev->dev,
+ fpga->regmap,
+ fldconf);
+ if (IS_ERR(pin->enbit))
+ return PTR_ERR(pin->enbit);
+
+ fldconf.reg = UPFPGA_REG_GPIO_DIR0 + regoff;
+ fldconf.lsb = lsb;
+ fldconf.msb = lsb;
+
+ pin->dirbit = devm_regmap_field_alloc(&pdev->dev,
+ fpga->regmap,
+ fldconf);
+ if (IS_ERR(pin->dirbit))
+ return PTR_ERR(pin->dirbit);
+
+ pd->drv_data = pin;
+
+ /* set output by default */
+ regmap_field_write(pin->dirbit, false);
+ }
+
+ /* create a new pinctrl device and register it */
+ pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
+ pctrl->regmap = fpga->regmap;
+ pctrl->rpi_mapping = rpi_mapping;
+ pctrl->chip = upboard_gpio_chip;
+ pctrl->pctldesc = pctldesc;
+ pctrl->chip.parent = &pdev->dev;
+ pctrl->chip.ngpio = ngpio;
+ pctrl->pins = pins;
+
+ ret = devm_gpiochip_add_data(&pdev->dev, &pctrl->chip, pctrl);
+ if (ret)
+ return ret;
+
+ pctrl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, pctrl);
+ if (IS_ERR(pctrl->pctldev))
+ return PTR_ERR(pctrl->pctldev);
+
+ /* add acpi pin mapping according to external-gpios key */
+ ret = upboard_acpi_node_pin_mapping(fpga, pctrl,
+ "external",
+ dev_name(&pdev->dev),
+ 0);
+ if (ret)
+ return ret;
+
+ /* check for special board versions that require register patches */
+ system_id = dmi_first_match(upboard_dmi_table);
+ if (system_id)
+ pctrl->ident = system_id->ident;
+ else
+ pctrl->ident = BOARD_UP_APL03;
+
+ upboard_alt_func_enable(&pctrl->chip, "I2C", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "SPI", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "SPI1", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "SPI2", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "UART", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "I2S", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "PWM", pctrl->ident);
+ upboard_alt_func_enable(&pctrl->chip, "ADC", pctrl->ident);
+ /* I2C pin mux by CPLD in UP2 */
+ upboard_alt_func_enable(&pctrl->chip, "NONAME", pctrl->ident);
+
+ return ret;
+}
+
+static struct platform_driver upboard_pinctrl_driver = {
+ .driver = {
+ .name = "upboard-pinctrl",
+ },
+};
+module_platform_driver_probe(upboard_pinctrl_driver, upboard_pinctrl_probe);
+
+MODULE_AUTHOR("Gary Wang <garywang@aaeon.com.tw>");
+MODULE_DESCRIPTION("UP Board HAT pin controller driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:upboard-pinctrl");
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS
2023-04-25 15:21 [RFC RESEND 0/3] Add support control UP board CPLD/FPGA pin control larry.lai
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
2023-04-25 15:21 ` [RFC RESEND 2/3] pinctrl: Add support pin control " larry.lai
@ 2023-04-25 15:21 ` larry.lai
2023-04-27 17:15 ` Lee Jones
2 siblings, 1 reply; 9+ messages in thread
From: larry.lai @ 2023-04-25 15:21 UTC (permalink / raw)
To: lee, andriy.shevchenko, linus.walleij, pavel
Cc: linux-kernel, linux-gpio, linux-leds, GaryWang, musa.lin,
jack.chang, noah.hung, michael.wang, larry.lai
The UP boards come with a few FPGA-controlled onboard LEDs:
* UP Board: yellow, green, red
* UP Squared: blue, yellow, green, red
This patch depends on patch "mfd: Add support for UP board CPLD/FPGA".
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Lee Jones <lee@kernel.org>
Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
---
RFC 2022/11/23 --> RFC 2023/04/25: Refer 2022/12/08 Lee Jones review,
cleaned up coding style.
PATCH V3 -> RFC 2022/11/23: Update the changes Copyright.
PATCH V1 -> V3: There is no change.
PATCH --> PATCH V1: Refer 2022/10/03 Andy Shevchenko review, cleaned up
coding style.
---
---
drivers/leds/Kconfig | 10 +++++
drivers/leds/Makefile | 1 +
drivers/leds/leds-upboard.c | 79 +++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+)
create mode 100644 drivers/leds/leds-upboard.c
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 499d0f215a8b..d9d533cb38ca 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -872,6 +872,16 @@ source "drivers/leds/flash/Kconfig"
comment "RGB LED drivers"
source "drivers/leds/rgb/Kconfig"
+config LEDS_UPBOARD
+ tristate "LED support for the UP board"
+ depends on LEDS_CLASS
+ depends on MFD_INTEL_UPBOARD_FPGA
+ help
+ This option enables support for the UP board LEDs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called leds-upboard.
+
comment "LED Triggers"
source "drivers/leds/trigger/Kconfig"
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 4fd2f92cd198..e72956645646 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_LEDS_TI_LMU_COMMON) += leds-ti-lmu-common.o
obj-$(CONFIG_LEDS_TLC591XX) += leds-tlc591xx.o
obj-$(CONFIG_LEDS_TPS6105X) += leds-tps6105x.o
obj-$(CONFIG_LEDS_TURRIS_OMNIA) += leds-turris-omnia.o
+obj-$(CONFIG_LEDS_UPBOARD) += leds-upboard.o
obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o
obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o
obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
diff --git a/drivers/leds/leds-upboard.c b/drivers/leds/leds-upboard.c
new file mode 100644
index 000000000000..8a44afe8c526
--- /dev/null
+++ b/drivers/leds/leds-upboard.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UP Board CPLD/FPGA based LED driver
+ *
+ * Copyright (c) AAEON. All rights reserved.
+ *
+ * Author: Gary Wang <garywang@aaeon.com.tw>
+ */
+
+#include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/mfd/upboard-fpga.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+struct upboard_led {
+ struct regmap_field *field;
+ struct led_classdev cdev;
+ unsigned char bit;
+};
+
+static enum led_brightness upboard_led_brightness_get(struct led_classdev *cdev)
+{
+ struct upboard_led *led = container_of(cdev, struct upboard_led, cdev);
+ int brightness = 0;
+
+ regmap_field_read(led->field, &brightness);
+
+ return brightness;
+};
+
+static void upboard_led_brightness_set(struct led_classdev *cdev, enum led_brightness brightness)
+{
+ struct upboard_led *led = container_of(cdev, struct upboard_led, cdev);
+
+ regmap_field_write(led->field, brightness != LED_OFF);
+};
+
+static int __init upboard_led_probe(struct platform_device *pdev)
+{
+ struct upboard_fpga * const up_fpga = dev_get_drvdata(pdev->dev.parent);
+ struct reg_field fldconf = {
+ .reg = UPFPGA_REG_FUNC_EN0,
+ };
+ struct upboard_led_data * const pdata = pdev->dev.platform_data;
+ struct upboard_led *led;
+
+ led = devm_kzalloc(&pdev->dev, sizeof(*led), GFP_KERNEL);
+ if (!led)
+ return -ENOMEM;
+
+ fldconf.lsb = pdata->bit;
+ fldconf.msb = pdata->bit;
+ led->field = devm_regmap_field_alloc(&pdev->dev, up_fpga->regmap, fldconf);
+ if (IS_ERR(led->field))
+ return PTR_ERR(led->field);
+
+ led->cdev.brightness_get = upboard_led_brightness_get;
+ led->cdev.brightness_set = upboard_led_brightness_set;
+ led->cdev.name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "upboard:%s:",
+ pdata->colour);
+ if (!led->cdev.name)
+ return -ENOMEM;
+
+ return devm_led_classdev_register(&pdev->dev, &led->cdev);
+};
+
+static struct platform_driver upboard_led_driver = {
+ .driver = {
+ .name = "upboard-led",
+ },
+};
+module_platform_driver_probe(upboard_led_driver, upboard_led_probe);
+
+MODULE_AUTHOR("Gary Wang <garywang@aaeon.com.tw>");
+MODULE_DESCRIPTION("UP Board LED driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:upboard-led");
--
2.17.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
@ 2023-04-27 17:14 ` Lee Jones
2023-05-02 4:56 ` kernel test robot
2023-05-02 14:21 ` kernel test robot
2 siblings, 0 replies; 9+ messages in thread
From: Lee Jones @ 2023-04-27 17:14 UTC (permalink / raw)
To: larry.lai
Cc: andriy.shevchenko, linus.walleij, pavel, linux-kernel, linux-gpio,
linux-leds, GaryWang, musa.lin, jack.chang, noah.hung,
michael.wang, Javier Arteaga, Nicola Lunghi
On Tue, 25 Apr 2023, larry.lai wrote:
> The UP Squared board <http://www.upboard.com> implements certain
> features (pin control, onboard LEDs or CEC) through an on-board CPLD/FPGA.
>
> This mfd driver implements the line protocol to read and write registers
> from the FPGA through regmap. The register address map is also included.
>
> The UP Boards provide a few I/O pin headers (for both GPIO and
> functions), including a 40-pin Raspberry Pi compatible header.
>
> This patch implements support for the FPGA-based pin controller that
> manages direction and enable state for those header pins.
>
> Partial support UP boards:
> * UP core + CREX
> * UP core + CRST02
>
> Signed-off-by: Javier Arteaga <javier@emutex.com>
> [merge various fixes]
> Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
> Reviewed-by: Lee Jones <lee@kernel.org>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Wait, what?!
When did Andy or I provide you with Reviewed-by tags?
You must to apply any tag that isn't explicitly provided to you.
> Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
> ---
> RFC 2022/11/23 -> RFC 2023/04/25
> (1) Refer 2022/12/08 Andy Shevchenko review, cleaned up coding style
> and addressed review comments.
> PATCH V3 -> RFC 2022/11/23:
> (1) Refer 2022/11/16 Lee Jones review, cleaned up coding style and
> addressed review comments.
> (2) Description on the UP Boards FPGA register read/write protocols
> PATCH V2 -> V3:
> (1) fixed kernel test robot compiler warning
> PATCH V1 -> V2:
> (1) Synchronizing upboard github to rc2
> (2) Refer 2022/10/31 Lee Jones review, fixed some of the issues.
> ---
> ---
> drivers/mfd/Kconfig | 12 +
> drivers/mfd/Makefile | 1 +
> drivers/mfd/upboard-fpga.c | 527 +++++++++++++++++++++++++++++++
> include/linux/mfd/upboard-fpga.h | 61 ++++
> 4 files changed, 601 insertions(+)
> create mode 100644 drivers/mfd/upboard-fpga.c
> create mode 100644 include/linux/mfd/upboard-fpga.h
I'm not even going to try and review this (again).
Looking at the subject line, this is patch is masquerading as a RESEND
of an unreviewed v1. However, at best this is a RESEND of a reviewed
(which was ignored) v3, perhaps even just a straight v4.
Either way, it appears as though the review comments you received in v3
were ignored. Please go back and fix those before submitting v5,
thanks.
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS
2023-04-25 15:21 ` [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS larry.lai
@ 2023-04-27 17:15 ` Lee Jones
0 siblings, 0 replies; 9+ messages in thread
From: Lee Jones @ 2023-04-27 17:15 UTC (permalink / raw)
To: larry.lai
Cc: andriy.shevchenko, linus.walleij, pavel, linux-kernel, linux-gpio,
linux-leds, GaryWang, musa.lin, jack.chang, noah.hung,
michael.wang
On Tue, 25 Apr 2023, larry.lai wrote:
> The UP boards come with a few FPGA-controlled onboard LEDs:
> * UP Board: yellow, green, red
> * UP Squared: blue, yellow, green, red
>
> This patch depends on patch "mfd: Add support for UP board CPLD/FPGA".
>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Reviewed-by: Lee Jones <lee@kernel.org>
Definitely not. Please try again after reading:
Documentation/process/submitting-patches.rst
> Signed-off-by: larry.lai <larry.lai@yunjingtech.com>
> ---
> RFC 2022/11/23 --> RFC 2023/04/25: Refer 2022/12/08 Lee Jones review,
> cleaned up coding style.
> PATCH V3 -> RFC 2022/11/23: Update the changes Copyright.
> PATCH V1 -> V3: There is no change.
> PATCH --> PATCH V1: Refer 2022/10/03 Andy Shevchenko review, cleaned up
> coding style.
> ---
> ---
> drivers/leds/Kconfig | 10 +++++
> drivers/leds/Makefile | 1 +
> drivers/leds/leds-upboard.c | 79 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 90 insertions(+)
> create mode 100644 drivers/leds/leds-upboard.c
--
Lee Jones [李琼斯]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
2023-04-27 17:14 ` Lee Jones
@ 2023-05-02 4:56 ` kernel test robot
2023-05-02 14:21 ` kernel test robot
2 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2023-05-02 4:56 UTC (permalink / raw)
To: larry.lai; +Cc: llvm, oe-kbuild-all
Hi larry.lai,
[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:
[auto build test WARNING on 4fe89d07dcc2804c8b562f6c7896a45643d34b2f]
url: https://github.com/intel-lab-lkp/linux/commits/larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
base: 4fe89d07dcc2804c8b562f6c7896a45643d34b2f
patch link: https://lore.kernel.org/r/20230425152135.30745-2-larry.lai%40yunjingtech.com
patch subject: [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20230502/202305021237.3KjZn3Ga-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/cb16ef420038f2bede2deb3878b529f0e6ea7729
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
git checkout cb16ef420038f2bede2deb3878b529f0e6ea7729
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/firmware/ drivers/hwmon/ drivers/mfd/ drivers/pinctrl/ drivers/staging/media/atomisp/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305021237.3KjZn3Ga-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/mfd/upboard-fpga.c:448:49: warning: data argument not used by format string [-Wformat-extra-args]
dev_err(fpga->dev, "Failed to add GPIO LEDs", ret);
~~~~~~~~~~~~~~~~~~~~~~~~~ ^
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^
drivers/mfd/upboard-fpga.c:486:20: error: assigning to 'struct regmap_config *' from 'const struct regmap_config *const' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
fpga->cpld_config = fpga_data->cpld_config;
^ ~~~~~~~~~~~~~~~~~~~~~~
1 warning and 1 error generated.
vim +448 drivers/mfd/upboard-fpga.c
383
384 /*
385 * MFD upboard-fpga is ACPI driver and can recognize the AANT ID from different
386 * kind of upboards. We get the LED GPIO initialized information from this
387 * then add led-upboard driver.
388 */
389 int upboard_led_gpio_register(struct upboard_fpga *fpga)
390 {
391 struct gpio_led blue_led, yellow_led, green_led, red_led;
392 struct gpio_desc *desc;
393 static struct gpio_led upboard_gpio_leds[4];
394 int leds = 0;
395 static struct gpio_led_platform_data upboard_gpio_led_platform_data;
396 static const struct mfd_cell upboard_gpio_led_cells[] = {
397 MFD_CELL_BASIC("leds-gpio", NULL,
398 &upboard_gpio_led_platform_data,
399 sizeof(upboard_gpio_led_platform_data), 0)
400 };
401 int ret;
402
403 desc = devm_gpiod_get(fpga->dev, "blue", GPIOD_OUT_LOW);
404 if (!IS_ERR(desc)) {
405 blue_led.name = "upboard:blue:";
406 blue_led.gpio = desc_to_gpio(desc);
407 blue_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
408 upboard_gpio_leds[leds++] = blue_led;
409 devm_gpiod_put(fpga->dev, desc);
410 }
411 desc = devm_gpiod_get(fpga->dev, "yellow", GPIOD_OUT_LOW);
412 if (!IS_ERR(desc)) {
413 yellow_led.name = "upboard:yellow:";
414 yellow_led.gpio = desc_to_gpio(desc);
415 yellow_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
416 upboard_gpio_leds[leds++] = yellow_led;
417 devm_gpiod_put(fpga->dev, desc);
418 }
419 desc = devm_gpiod_get(fpga->dev, "green", GPIOD_OUT_LOW);
420 if (!IS_ERR(desc)) {
421 green_led.name = "upboard:green:";
422 green_led.gpio = desc_to_gpio(desc);
423 green_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
424 upboard_gpio_leds[leds++] = green_led;
425 devm_gpiod_put(fpga->dev, desc);
426 }
427 desc = devm_gpiod_get(fpga->dev, "red", GPIOD_OUT_LOW);
428 if (!IS_ERR(desc)) {
429 red_led.name = "upboard:red:";
430 red_led.gpio = desc_to_gpio(desc);
431 red_led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
432 upboard_gpio_leds[leds++] = red_led;
433 devm_gpiod_put(fpga->dev, desc);
434 }
435
436 /* no LEDs */
437 if (leds == 0)
438 return 0;
439
440 upboard_gpio_led_platform_data.num_leds = leds;
441 upboard_gpio_led_platform_data.leds = upboard_gpio_leds;
442
443 ret = devm_mfd_add_devices(fpga->dev, PLATFORM_DEVID_AUTO,
444 upboard_gpio_led_cells,
445 ARRAY_SIZE(upboard_gpio_led_cells),
446 NULL, 0, NULL);
447 if (ret) {
> 448 dev_err(fpga->dev, "Failed to add GPIO LEDs", ret);
449 return ret;
450 }
451
452 return 0;
453 }
454
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
2023-04-27 17:14 ` Lee Jones
2023-05-02 4:56 ` kernel test robot
@ 2023-05-02 14:21 ` kernel test robot
2 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2023-05-02 14:21 UTC (permalink / raw)
To: larry.lai; +Cc: llvm, oe-kbuild-all
Hi larry.lai,
[This is a private test report for your RFC patch.]
kernel test robot noticed the following build errors:
[auto build test ERROR on 4fe89d07dcc2804c8b562f6c7896a45643d34b2f]
url: https://github.com/intel-lab-lkp/linux/commits/larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
base: 4fe89d07dcc2804c8b562f6c7896a45643d34b2f
patch link: https://lore.kernel.org/r/20230425152135.30745-2-larry.lai%40yunjingtech.com
patch subject: [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20230502/202305022231.zyZXagsH-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/cb16ef420038f2bede2deb3878b529f0e6ea7729
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
git checkout cb16ef420038f2bede2deb3878b529f0e6ea7729
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305022231.zyZXagsH-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/mfd/upboard-fpga.c:448:49: warning: data argument not used by format string [-Wformat-extra-args]
dev_err(fpga->dev, "Failed to add GPIO LEDs", ret);
~~~~~~~~~~~~~~~~~~~~~~~~~ ^
include/linux/dev_printk.h:144:65: note: expanded from macro 'dev_err'
dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__)
~~~ ^
include/linux/dev_printk.h:110:23: note: expanded from macro 'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__); \
~~~ ^
>> drivers/mfd/upboard-fpga.c:486:20: error: assigning to 'struct regmap_config *' from 'const struct regmap_config *const' discards qualifiers [-Werror,-Wincompatible-pointer-types-discards-qualifiers]
fpga->cpld_config = fpga_data->cpld_config;
^ ~~~~~~~~~~~~~~~~~~~~~~
1 warning and 1 error generated.
vim +486 drivers/mfd/upboard-fpga.c
465
466 static int __init upboard_fpga_probe(struct platform_device *pdev)
467 {
468 struct upboard_fpga *fpga;
469 const struct acpi_device_id *id;
470 const struct upboard_fpga_data *fpga_data;
471 int ret;
472 struct device *dev = &pdev->dev;
473
474 id = acpi_match_device(upboard_fpga_acpi_match, dev);
475 if (!id)
476 return -ENODEV;
477
478 fpga_data = (const struct upboard_fpga_data *) id->driver_data;
479
480 fpga = devm_kzalloc(dev, sizeof(*fpga), GFP_KERNEL);
481 if (!fpga)
482 return -ENOMEM;
483
484 platform_set_drvdata(pdev, fpga);
485 fpga->regmap = devm_regmap_init(dev, NULL, fpga, fpga_data->cpld_config);
> 486 fpga->cpld_config = fpga_data->cpld_config;
487
488 if (IS_ERR(fpga->regmap))
489 return PTR_ERR(fpga->regmap);
490
491 ret = upboard_fpga_gpio_init(fpga);
492 if (ret) {
493 /*
494 * This is for compatiable with some upboards w/o FPGA firmware,
495 * so just showing debug info and do not return directly.
496 */
497 dev_warn(dev, "Failed to initialize FPGA common GPIOs: %d", ret);
498 } else {
499 upboard_fpga_show_firmware_info(fpga);
500 }
501
502 /* register GPIO LEDs */
503 ret = upboard_led_gpio_register(fpga);
504 if (ret) {
505 /*
506 * This is for compatiable with some upboards w/o LEDs.
507 */
508 dev_warn(dev, "Failed to register LEDs: %d", ret);
509 }
510
511 return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
512 fpga_data->cells,
513 fpga_data->ncells,
514 NULL, 0, NULL);
515 }
516
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [RFC RESEND 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA
2023-04-25 15:21 ` [RFC RESEND 2/3] pinctrl: Add support pin control " larry.lai
@ 2023-05-02 17:37 ` kernel test robot
0 siblings, 0 replies; 9+ messages in thread
From: kernel test robot @ 2023-05-02 17:37 UTC (permalink / raw)
To: larry.lai; +Cc: llvm, oe-kbuild-all
Hi larry.lai,
[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:
[auto build test WARNING on 4fe89d07dcc2804c8b562f6c7896a45643d34b2f]
url: https://github.com/intel-lab-lkp/linux/commits/larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
base: 4fe89d07dcc2804c8b562f6c7896a45643d34b2f
patch link: https://lore.kernel.org/r/20230425152135.30745-3-larry.lai%40yunjingtech.com
patch subject: [RFC RESEND 2/3] pinctrl: Add support pin control for UP board CPLD/FPGA
config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20230503/202305030144.WmuMog6A-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/b8c1c33f21a4a0526016b4ec803adabc2d32b035
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review larry-lai/mfd-Add-support-for-UP-board-CPLD-FPGA/20230425-232744
git checkout b8c1c33f21a4a0526016b4ec803adabc2d32b035
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash drivers/firmware/ drivers/hwmon/ drivers/pinctrl/ drivers/staging/media/atomisp/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Link: https://lore.kernel.org/oe-kbuild-all/202305030144.WmuMog6A-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pinctrl/pinctrl-upboard.c:754:13: warning: variable length array used [-Wvla]
int offset[pctrl->pctldesc->npins];
^~~~~~~~~~~~~~~~~~~~~~
>> drivers/pinctrl/pinctrl-upboard.c:774:8: warning: mixing declarations and code is incompatible with standards before C99 [-Wdeclaration-after-statement]
bool input = false;
^
>> drivers/pinctrl/pinctrl-upboard.c:877:26: warning: unused variable 'pctrl' [-Wunused-variable]
struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
^
drivers/pinctrl/pinctrl-upboard.c:888:19: warning: variable length array used [-Wvla]
char name[strlen(pctrl->pctldesc->pins[pin].name)];
~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pinctrl/pinctrl-upboard.c:1009:5: warning: no previous prototype for function 'upboard_acpi_node_pin_mapping' [-Wmissing-prototypes]
int upboard_acpi_node_pin_mapping(struct upboard_fpga *fpga,
^
drivers/pinctrl/pinctrl-upboard.c:1009:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
int upboard_acpi_node_pin_mapping(struct upboard_fpga *fpga,
^
static
>> drivers/pinctrl/pinctrl-upboard.c:1068:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UP_APL03,
^~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:85:26: note: expanded from macro 'BOARD_UP_APL03'
#define BOARD_UP_APL03 9
^
drivers/pinctrl/pinctrl-upboard.c:1075:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UP_WHL01,
^~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:82:26: note: expanded from macro 'BOARD_UP_WHL01'
#define BOARD_UP_WHL01 5
^
drivers/pinctrl/pinctrl-upboard.c:1082:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPX_TGL,
^~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:87:25: note: expanded from macro 'BOARD_UPX_TGL'
#define BOARD_UPX_TGL 11
^~
drivers/pinctrl/pinctrl-upboard.c:1089:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPN_EHL01,
^~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:89:27: note: expanded from macro 'BOARD_UPN_EHL01'
#define BOARD_UPN_EHL01 13
^~
drivers/pinctrl/pinctrl-upboard.c:1096:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPS_EHL01,
^~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:90:27: note: expanded from macro 'BOARD_UPS_EHL01'
#define BOARD_UPS_EHL01 14
^~
drivers/pinctrl/pinctrl-upboard.c:1103:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPX_ADLP01,
^~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:91:27: note: expanded from macro 'BOARD_UPX_ADLP01'
#define BOARD_UPX_ADLP01 15
^~
drivers/pinctrl/pinctrl-upboard.c:1110:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPN_ADLN01,
^~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:92:27: note: expanded from macro 'BOARD_UPN_ADLN01'
#define BOARD_UPN_ADLN01 16
^~
drivers/pinctrl/pinctrl-upboard.c:1117:12: warning: incompatible integer to pointer conversion initializing 'const char *' with an expression of type 'int' [-Wint-conversion]
.ident = BOARD_UPS_ADLP01,
^~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:93:27: note: expanded from macro 'BOARD_UPS_ADLP01'
#define BOARD_UPS_ADLP01 15
^~
>> drivers/pinctrl/pinctrl-upboard.c:1253:16: warning: incompatible pointer to integer conversion assigning to 'int' from 'const char *const' [-Wint-conversion]
pctrl->ident = system_id->ident;
^ ~~~~~~~~~~~~~~~~
drivers/pinctrl/pinctrl-upboard.c:298:38: warning: unused variable 'pin_groups' [-Wunused-const-variable]
static const struct upboard_pingroup pin_groups[] = {
^
drivers/pinctrl/pinctrl-upboard.c:320:38: warning: unused variable 'pin_functions' [-Wunused-const-variable]
static const struct upboard_function pin_functions[] = {
^
16 warnings generated.
vim +754 drivers/pinctrl/pinctrl-upboard.c
750
751 static void upboard_alt_func_enable(struct gpio_chip *gc, const char *name, int id)
752 {
753 struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
> 754 int offset[pctrl->pctldesc->npins];
755 int i, cnt;
756
757 /* find all pins */
758 for (i = 0, cnt = 0; i < pctrl->pctldesc->npins; i++) {
759 if (strstr(pctrl->pctldesc->pins[i].name, name))
760 offset[cnt++] = i;
761 }
762
763 for (i = 0; i < cnt; i++) {
764 if (pinctrl_gpio_request(pctrl->pins[offset[i]].gpio))
765 return; /* this pin is being used */
766
767 pinctrl_gpio_free(pctrl->pins[offset[i]].gpio);
768 }
769
770 /* change to alternate function */
771 for (i = 0; i < cnt; i++) {
772 if (pctrl->pins[offset[i]].regs == NULL)
773 continue;
> 774 bool input = false;
775 int mode = 1; /* default */
776 unsigned int val = readl(pctrl->pins[offset[i]].regs);
777
778 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "I2C")) {
779 switch (id) {
780 case BOARD_UPN_ADLN01:
781 case BOARD_UPX_ADLP01:
782 mode = 2;
783 break;
784 default:
785 break;
786 }
787 val |= mode<<PADCFG0_PMODE_SHIFT;
788 writel(val, pctrl->pins[offset[i]].regs);
789 upboard_fpga_request_free(pctrl->pctldev, offset[i]);
790 continue;
791 } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "UART")) {
792 switch (id) {
793 case BOARD_UPN_EHL01:
794 case BOARD_UPS_EHL01:
795 mode = 4;
796 break;
797 case BOARD_UPN_ADLN01:
798 case BOARD_UPX_ADLP01:
799 mode = 2;
800 break;
801 default:
802 break;
803 }
804 } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "SPI")) {
805 switch (id) {
806 case BOARD_UP_WHL01:
807 mode = 3;
808 break;
809 case BOARD_UPN_ADLN01:
810 case BOARD_UPX_ADLP01:
811 mode = 7;
812 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MOSI")) {
813 val &= ~PADCFG0_GPIOTXDIS;
814 val |= PADCFG0_GPIORXDIS;
815 }
816 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MISO")) {
817 val |= PADCFG0_GPIORXDIS;
818 }
819 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CLK")) {
820 val &= ~PADCFG0_GPIOTXDIS;
821 val |= PADCFG0_GPIORXDIS;
822 }
823 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CS0")) {
824 val |= PADCFG0_GPIORXDIS;
825 }
826 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CS1")) {
827 continue;
828 }
829 break;
830 default:
831 break;
832 }
833 } else if (strstr(pctrl->pctldesc->pins[offset[i]].name, "I2S")) {
834 switch (id) {
835 case BOARD_UPX_ADLP01:
836 mode = 4;
837 break;
838 default:
839 break;
840 }
841 }
842 val |= mode<<PADCFG0_PMODE_SHIFT;
843 writel(val, pctrl->pins[offset[i]].regs);
844
845 /* input pins */
846 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "RX"))
847 input = true;
848 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "CTS"))
849 input = true;
850 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "ADC"))
851 input = true;
852 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "MISO"))
853 input = true;
854 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "DIN"))
855 input = true;
856 if (strstr(pctrl->pctldesc->pins[offset[i]].name, "SDI"))
857 input = true;
858 upboard_fpga_set_direction(pctrl->pctldev, NULL, offset[i], input);
859 }
860 }
861
862 static int upboard_rpi_to_native_gpio(struct gpio_chip *gc, unsigned int gpio)
863 {
864 struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
865 unsigned int pin = pctrl->rpi_mapping[gpio];
866 struct pinctrl_gpio_range *range;
867
868 range = pinctrl_find_gpio_range_from_pin(pctrl->pctldev, pin);
869 if (!range)
870 return -ENODEV;
871
872 return range->base;
873 }
874
875 static int upboard_gpio_request(struct gpio_chip *gc, unsigned int offset)
876 {
> 877 struct upboard_pinctrl *pctrl = container_of(gc, struct upboard_pinctrl, chip);
878 int gpio = upboard_rpi_to_native_gpio(gc, offset);
879
880 return pinctrl_gpio_request(gpio);
881 }
882
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-05-02 17:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-04-25 15:21 [RFC RESEND 0/3] Add support control UP board CPLD/FPGA pin control larry.lai
2023-04-25 15:21 ` [RFC RESEND 1/3] mfd: Add support for UP board CPLD/FPGA larry.lai
2023-04-27 17:14 ` Lee Jones
2023-05-02 4:56 ` kernel test robot
2023-05-02 14:21 ` kernel test robot
2023-04-25 15:21 ` [RFC RESEND 2/3] pinctrl: Add support pin control " larry.lai
2023-05-02 17:37 ` kernel test robot
2023-04-25 15:21 ` [RFC RESEND 3/3] leds: Add support for UP board CPLD onboard LEDS larry.lai
2023-04-27 17:15 ` Lee Jones
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