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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-acpi@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
	<rafael@kernel.org>, <lenb@kernel.org>,
	<dan.j.williams@intel.com>, <ira.weiny@intel.com>,
	<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
	<lukas@wunner.de>
Subject: Re: [PATCH 1/4] acpi: numa: Create enum for memory_target access coordinates indexing
Date: Fri, 12 May 2023 16:43:32 +0100	[thread overview]
Message-ID: <20230512164332.00002171@Huawei.com> (raw)
In-Reply-To: <168333151653.2290593.15815859836381468990.stgit@djiang5-mobl3>

On Fri, 05 May 2023 17:05:16 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Create enums to provide named indexing for the access coordinate array.
> This is in preparation for adding generic port support which will add a
> third index in the array to keep the generic port attributes separate from
> the memory attributes.
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>



> ---
>  drivers/acpi/numa/hmat.c |   35 ++++++++++++++++++++++++-----------
>  1 file changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
> index f9ff992038fa..abed728bf09d 100644
> --- a/drivers/acpi/numa/hmat.c
> +++ b/drivers/acpi/numa/hmat.c
> @@ -57,12 +57,18 @@ struct target_cache {
>  	struct node_cache_attrs cache_attrs;
>  };
>  
> +enum {
> +	NODE_ACCESS_CLASS_0 = 0,
> +	NODE_ACCESS_CLASS_1,
> +	NODE_ACCESS_CLASS_MAX,
> +};
> +
>  struct memory_target {
>  	struct list_head node;
>  	unsigned int memory_pxm;
>  	unsigned int processor_pxm;
>  	struct resource memregions;
> -	struct access_coordinate coord[2];
> +	struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];
>  	struct list_head caches;
>  	struct node_cache_attrs cache_attrs;
>  	bool registered;
> @@ -338,10 +344,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
>  			if (mem_hier == ACPI_HMAT_MEMORY) {
>  				target = find_mem_target(targs[targ]);
>  				if (target && target->processor_pxm == inits[init]) {
> -					hmat_update_target_access(target, type, value, 0);
> +					hmat_update_target_access(target, type, value,
> +								  NODE_ACCESS_CLASS_0);
>  					/* If the node has a CPU, update access 1 */
>  					if (node_state(pxm_to_node(inits[init]), N_CPU))
> -						hmat_update_target_access(target, type, value, 1);
> +						hmat_update_target_access(target, type, value,
> +									  NODE_ACCESS_CLASS_1);
>  				}
>  			}
>  		}
> @@ -600,10 +608,12 @@ static void hmat_register_target_initiators(struct memory_target *target)
>  	 */
>  	if (target->processor_pxm != PXM_INVAL) {
>  		cpu_nid = pxm_to_node(target->processor_pxm);
> -		register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
> +		register_memory_node_under_compute_node(mem_nid, cpu_nid,
> +							NODE_ACCESS_CLASS_0);
>  		access0done = true;
>  		if (node_state(cpu_nid, N_CPU)) {
> -			register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
> +			register_memory_node_under_compute_node(mem_nid, cpu_nid,
> +								NODE_ACCESS_CLASS_1);
>  			return;
>  		}
>  	}
> @@ -644,12 +654,13 @@ static void hmat_register_target_initiators(struct memory_target *target)
>  			}
>  			if (best)
>  				hmat_update_target_access(target, loc->hmat_loc->data_type,
> -							  best, 0);
> +							  best, NODE_ACCESS_CLASS_0);
>  		}
>  
>  		for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
>  			cpu_nid = pxm_to_node(i);
> -			register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
> +			register_memory_node_under_compute_node(mem_nid, cpu_nid,
> +								NODE_ACCESS_CLASS_0);
>  		}
>  	}
>  
> @@ -681,11 +692,13 @@ static void hmat_register_target_initiators(struct memory_target *target)
>  				clear_bit(initiator->processor_pxm, p_nodes);
>  		}
>  		if (best)
> -			hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1);
> +			hmat_update_target_access(target, loc->hmat_loc->data_type, best,
> +						  NODE_ACCESS_CLASS_1);
>  	}
>  	for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
>  		cpu_nid = pxm_to_node(i);
> -		register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
> +		register_memory_node_under_compute_node(mem_nid, cpu_nid,
> +							NODE_ACCESS_CLASS_1);
>  	}
>  }
>  
> @@ -746,8 +759,8 @@ static void hmat_register_target(struct memory_target *target)
>  	if (!target->registered) {
>  		hmat_register_target_initiators(target);
>  		hmat_register_target_cache(target);
> -		hmat_register_target_perf(target, 0);
> -		hmat_register_target_perf(target, 1);
> +		hmat_register_target_perf(target, NODE_ACCESS_CLASS_0);
> +		hmat_register_target_perf(target, NODE_ACCESS_CLASS_1);
>  		target->registered = true;
>  	}
>  	mutex_unlock(&target_lock);
> 
> 


  reply	other threads:[~2023-05-12 15:43 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-06  0:05 [PATCH 0/4] acpi: numa: add target support for generic port to HMAT parsing Dave Jiang
2023-05-06  0:05 ` [PATCH 1/4] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-05-12 15:43   ` Jonathan Cameron [this message]
2023-05-06  0:05 ` [PATCH 2/4] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-05-12 16:00   ` Jonathan Cameron
2023-05-06  0:05 ` [PATCH 3/4] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-05-12 16:10   ` Jonathan Cameron
2023-05-12 16:16   ` Jonathan Cameron
2023-05-12 16:22     ` Dave Jiang
2023-05-06  0:05 ` [PATCH 4/4] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-05-12 16:25   ` Jonathan Cameron

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