From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>
Subject: Re: [PATCH v6 04/11] cxl: Add support for _DSM Function for retrieving QTG ID
Date: Thu, 25 May 2023 17:44:12 +0100 [thread overview]
Message-ID: <20230525174412.00000783@Huawei.com> (raw)
In-Reply-To: <168451601833.3470703.277986088556971387.stgit@djiang5-mobl3>
On Fri, 19 May 2023 10:06:58 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> CXL spec v3.0 9.17.3 CXL Root Device Specific Methods (_DSM)
>
> Add support to retrieve QTG ID via ACPI _DSM call. The _DSM call requires
> an input of an ACPI package with 4 dwords (read latency, write latency,
> read bandwidth, write bandwidth). The call returns a package with 1 WORD
> that provides the max supported QTG ID and a package that may contain 0 or
> more WORDs as the recommended QTG IDs in the recommended order.
>
> Create a cxl_root container for the root cxl_port and provide a callback
> ->get_qos_class() in order to retrieve the QoS class. For the ACPI case,
> the _DSM helper is used to retrieve the QTG ID and returned. A
> devm_cxl_add_root() function is added for root port setup and registration
> of the cxl_root callback operation(s).
>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> caluclate
>
> caculates
?
> ---
next prev parent reply other threads:[~2023-05-25 16:44 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 17:06 [PATCH v6 00/11] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-05-19 17:06 ` [PATCH v6 01/11] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-05-25 16:43 ` Jonathan Cameron
2023-05-19 17:06 ` [PATCH v6 02/11] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 03/11] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-05-19 17:06 ` [PATCH v6 04/11] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-05-25 16:44 ` Jonathan Cameron [this message]
2023-05-25 21:09 ` Dave Jiang
2023-05-19 17:07 ` [PATCH v6 05/11] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 06/11] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-06-01 14:20 ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 07/11] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-05-19 17:07 ` [PATCH v6 08/11] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-05-19 17:07 ` [PATCH v6 09/11] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-06-01 14:32 ` Jonathan Cameron
2023-05-19 17:07 ` [PATCH v6 10/11] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-06-01 14:30 ` Jonathan Cameron
2023-06-01 17:13 ` Dave Jiang
2023-05-19 17:07 ` [PATCH v6 11/11] cxl/mem: Add debugfs output for QTG related data Dave Jiang
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