From: David Clear <dclear@amd.com>
To: <catalin.marinas@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>, <ardb@kernel.org>,
<mark.rutland@arm.com>, <maz@kernel.org>, <will@kernel.org>
Subject: Re: ARM64: Question: How to map non-shareable memory
Date: Thu, 25 May 2023 16:47:02 -0700 [thread overview]
Message-ID: <20230525234702.53202-1-dclear@amd.com> (raw)
In-Reply-To: <ZG8co3v/TYllfHAv@arm.com>
On Thu, 25 May 2023 at 09:30:27, Catalin Marinas wrote:
> Hi David,
Hi Catalin, thanks for the detailed comments.
I'm finally coming around... The multi-core issues, and having to drop
into kernel mode for the DC IVAC eliminates any possible advantage
this avenue of investigation could have yielded.
> Your best bet is Normal Non-cacheable here.
Yes, we'll stay with Normal_NC. BTW the Cortex A72 issues these as
ReadNoSnoop / WriteNoSnoop, so that's why they made it through the NOC.
> On newer architecture
> versions Arm introduced ST64B/LD64B for similar performance reasons
> (FEAT_LS64 in Armv8.7) but I don't think there's hardware yet.
That's very interesting. Something to look forward to.
Thanks again for your time. Both you and Ard. I appreciate it.
Regards,
David.
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prev parent reply other threads:[~2023-05-25 23:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-24 21:07 ARM64: Question: How to map non-shareable memory David Clear
2023-05-24 21:59 ` Ard Biesheuvel
2023-05-25 0:33 ` David Clear
2023-05-25 8:30 ` Catalin Marinas
2023-05-25 23:47 ` David Clear [this message]
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