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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v8 5/5] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Fri, 2 Jun 2023 13:07:54 +0100 Message-ID: <20230602120754.23817-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230602120754.23817-1-ayan.kumar.halder@amd.com> References: <20230602120754.23817-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT036:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f447898-408e-4180-e65a-08db636247d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S6fWyp+mCtFeFEiSkt3ziO2w0TZswBwsT+abt9rmsuaW3rvUyELXKUSDp/tMrav6tJRAkTnG+t4ZCt43usBa8C31BERU2/7hQ555fq3DfeyavJcxUE3dEFKKWRyDGUeszCz8DL6RIjuzk7GxZB1de3Okwp2gsh2DnWRDicmtkfn85pgSks8lFk7CUxU0pVU6LOW3JHMhEvFES4XQjzZlgAZfXbEQwVYnriSbecJ0zkK01eXc8IEP/lm6tybjXliQ6yXVXBMGIPV7juAc1KWGyWBBiGPEdabsSqUKWqW63lxfFT8RXfiSoQxX98m6BpfllkBBFZSS+50OEEu1X/8VlhjbubrjjsDIn/RX0BoyWqq4TfcPv59K/Izea8KrFKoXex4YCn20uzsP7cUhxOxS5fqYjcRtWztdJRVnKPY8Uye49HwyZGXbwzohKCL+5W7NRyTDOWVjt2R/XmEhHPop6y0ZK6iFlwGIwWt0NS36cAFadcYottMwTg5paDv9wQ2RSzb9IKhtnb630QT0Y/PKTtl+x4QWnIpgpTCJvqa7O7H9gAMw02erdbYceMYOl19j0241GMlAepvyy9CmNbNFH33k6HAg5th4OWZbYIlhvhUhJHK6vzDs/GqCdYfb+cJTFr5BBstgu5rWPKCmg9+qeJ1ZzUrzQiBBjtmPn08S4bnrJ9nEagNdiHhHSMZ414g36LUeBLlNAKImye828aktWkOx/mACtP7nBZt4ydEIzdXJisgJKtext5Oj4m/sEGx+Koxf3yx/wOQTR8vB+/YL2w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199021)(40470700004)(36840700001)(46966006)(336012)(426003)(83380400001)(47076005)(40460700003)(103116003)(2616005)(2906002)(36756003)(86362001)(82310400005)(81166007)(356005)(82740400003)(36860700001)(40480700001)(316002)(5660300002)(4326008)(7416002)(41300700001)(478600001)(54906003)(8936002)(8676002)(186003)(6916009)(70206006)(70586007)(26005)(1076003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jun 2023 12:09:56.4730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5f447898-408e-4180-e65a-08db636247d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5605 Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. v4 - 1. t0sz is 0 for 32-bit IPA on Arm32. 2. Updated the commit message to explain t0sz, sl0 and root_order. v5 - 1. Rebased on top of the changes in the previous patch. v6 - 1. Removed the index for ARM_32. v7 - 1. No changes. xen/arch/arm/p2m.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 76388ba54b..a969068a68 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2265,6 +2265,7 @@ void __init setup_virt_paging(void) [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ #else + { 32, 0/*0*/, 0, 1 }, { 40, 24/*24*/, 1, 1 } #endif }; -- 2.17.1