[Intel-xe] [PATCH 0/2] Implement rcs/ccs missing invalidations and flushes

["Thomas Hellström" <thomas.hellstrom@linux.intel.com>]

Mesa is seeing unexpected content in some tests.
Fixing those require a TLB invalidation at batch start and a
render cache flush at batch end.

KMD also requires the latter to make sure any GPU side caches are
flushed before handing memory over for reuse. This is implemented
in patch 2.

The former is likely due to scratch PTEs remaining in the TLB after a
prefetch or similar. We could discuss whether user-space should be
responsible for a TLB invalidation after a VM_BIND operation, but
patch 1 implements a TLB flush at batch start for non-LR vms with scratch
pages. For LR vms with scratch pages the TLB flush is incoporated
in the bind fence.

The TLB invalidation can be optimized / coalesced later.

Thomas Hellström (2):
  drm/xe: Invalidate TLB also on bind if in scratch page mode
  drm/xe: Emit a render cache flush after each rcs/ccs batch

 drivers/gpu/drm/xe/regs/xe_gpu_commands.h |  4 ++
 drivers/gpu/drm/xe/xe_pt.c                | 17 +++++++-
 drivers/gpu/drm/xe/xe_ring_ops.c          | 50 +++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_wa_oob.rules        |  1 +
 4 files changed, 67 insertions(+), 5 deletions(-)

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2.39.2