From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03930C7EE25 for ; Thu, 8 Jun 2023 06:31:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3ED910E58A; Thu, 8 Jun 2023 06:31:03 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3552410E593 for ; Thu, 8 Jun 2023 06:31:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686205862; x=1717741862; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Eh8YyZ5wqzQOSWU6BPagtOC0CorxRe/dvdgAnnYI6k8=; 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charset=us-ascii Content-Disposition: inline In-Reply-To: <20230607094502.388489-1-stanislaw.gruszka@linux.intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Kacprowski , Oded Gabbay , Jeffrey Hugo , Jacek Lawrynowicz , Krystian Pradzynski Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Jun 07, 2023 at 11:45:02AM +0200, Stanislaw Gruszka wrote: > From: Andrzej Kacprowski > > Wait for AON bit in HOST_SS_CPR_RST_CLR to return 0 before > starting VPUIP power up sequence, otherwise the VPU device > may sporadically fail to boot. > > An error in power up sequence is propagated to the runtime > power management - the device will be in an error state > until the VPU driver is reloaded. > > Fixes: 35b137630f08 ("accel/ivpu: Introduce a new DRM driver for Intel VPU") > Cc: stable@vger.kernel.org # 6.3.x > Signed-off-by: Andrzej Kacprowski > Reviewed-by: Krystian Pradzynski > Signed-off-by: Stanislaw Gruszka Applied to drm-misc-fixes Thanks Stanislaw > --- > drivers/accel/ivpu/ivpu_hw_mtl.c | 13 ++++++++++++- > drivers/accel/ivpu/ivpu_hw_mtl_reg.h | 1 + > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/accel/ivpu/ivpu_hw_mtl.c b/drivers/accel/ivpu/ivpu_hw_mtl.c > index 382ec127be8e..efae679d7b7a 100644 > --- a/drivers/accel/ivpu/ivpu_hw_mtl.c > +++ b/drivers/accel/ivpu/ivpu_hw_mtl.c > @@ -197,6 +197,11 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) > hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio); > } > > +static int ivpu_hw_mtl_wait_for_vpuip_bar(struct ivpu_device *vdev) > +{ > + return REGV_POLL_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, AON, 0, 100); > +} > + > static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) > { > struct ivpu_hw_info *hw = vdev->hw; > @@ -239,6 +244,12 @@ static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) > ivpu_err(vdev, "Timed out waiting for PLL ready status\n"); > return ret; > } > + > + ret = ivpu_hw_mtl_wait_for_vpuip_bar(vdev); > + if (ret) { > + ivpu_err(vdev, "Timed out waiting for VPUIP bar\n"); > + return ret; > + } > } > > return 0; > @@ -256,7 +267,7 @@ static int ivpu_pll_disable(struct ivpu_device *vdev) > > static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev) > { > - u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR); > + u32 val = 0; > > val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val); > val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val); > diff --git a/drivers/accel/ivpu/ivpu_hw_mtl_reg.h b/drivers/accel/ivpu/ivpu_hw_mtl_reg.h > index d83ccfd9a871..593b8ff07417 100644 > --- a/drivers/accel/ivpu/ivpu_hw_mtl_reg.h > +++ b/drivers/accel/ivpu/ivpu_hw_mtl_reg.h > @@ -91,6 +91,7 @@ > #define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK BIT_MASK(11) > > #define MTL_VPU_HOST_SS_CPR_RST_CLR 0x00000098u > +#define MTL_VPU_HOST_SS_CPR_RST_CLR_AON_MASK BIT_MASK(0) > #define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK BIT_MASK(1) > #define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK BIT_MASK(10) > #define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK BIT_MASK(11) > -- > 2.25.1 >