From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2129C7EE25 for ; Thu, 8 Jun 2023 14:03:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236548AbjFHODK (ORCPT ); Thu, 8 Jun 2023 10:03:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234429AbjFHODH (ORCPT ); Thu, 8 Jun 2023 10:03:07 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9E1B198C; Thu, 8 Jun 2023 07:03:05 -0700 (PDT) X-GND-Sasl: miquel.raynal@bootlin.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1686232984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jnCroNGp1M+uiCnGqikYI4/3yHPp7dCX3+gK/nsGdo4=; b=nqSOFk2jprLAEjTEnhpb8ceq1s4cTV5qOWx+88Y2Vn/72O7rPjsM4hheBZi0/JxbG2luyg i39tWsQkL99tlDnOl8UBMuN5Tn+sY1ttnPjaADKJkSJzuhwKC4vgvIFgoxzVQPpWzmFjoH tN4qpTrjTtUYJgSPikJ0EgOno80gRxufPNVQYs+/0Ilhb56T//Cf/FohEG7kcQSTySXuEn JbUX/K5a8FI6ezkCOu8yWI4W6t6PAj9Z9yeRorB2cJdNgIBuHkfHjCjrkkUG1PJaTXKw9m b/Gu0uwclxezU1Ttb5MlDumZcsdJsNl91v/kv9HQkbTQQTakL3n+iose5SSklg== X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 0396DE000B; Thu, 8 Jun 2023 14:03:03 +0000 (UTC) Date: Thu, 8 Jun 2023 16:03:03 +0200 From: Miquel Raynal To: Md Sadre Alam Cc: mani@kernel.org, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com Subject: Re: [PATCH v3 4/5] mtd: rawnand: qcom: Add support for read, write, erase exec_ops Message-ID: <20230608160303.51ea70a6@xps-13> In-Reply-To: <20230531124953.21007-4-quic_mdalam@quicinc.com> References: <20230531124953.21007-1-quic_mdalam@quicinc.com> <20230531124953.21007-4-quic_mdalam@quicinc.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Md, quic_mdalam@quicinc.com wrote on Wed, 31 May 2023 18:19:52 +0530: > This change will add exec_ops support for READ, WRITE, and ERASE > command. >=20 > Co-developed-by: Sricharan Ramabadhran > Signed-off-by: Sricharan Ramabadhran > Signed-off-by: Md Sadre Alam > --- > Change in [v3] >=20 > * Removed chip->cont_read.ongoing flag. >=20 > * Removed pre_command from erase_etype_exec_ops. >=20 > Change in [v2] >=20 > * Missed to post Cover-letter, so posting v2 patch with cover-letter. >=20 > Change in [v1] >=20 > * Added initial support for exec_ops. >=20 > drivers/mtd/nand/raw/qcom_nandc.c | 97 +++++++++++++++++++++++++++++-- > 1 file changed, 93 insertions(+), 4 deletions(-) >=20 > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qco= m_nandc.c > index b4823b72fe73..7dc769f9e797 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -1546,8 +1546,7 @@ static void pre_command(struct qcom_nand_host *host= , int command) > =20 > clear_read_regs(nandc); > =20 > - if (command =3D=3D NAND_CMD_ERASE1) > - clear_bam_transaction(nandc); > + clear_bam_transaction(nandc); > } > =20 > /* > @@ -1764,7 +1763,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct= nand_chip *chip, > int ret, reg_off =3D FLASH_BUF_ACC, read_loc =3D 0; > int raw_cw =3D cw; > =20 > - nand_read_page_op(chip, page, 0, NULL, 0); > + nand_read_page_op(chip, page, 0, data_buf, mtd->writesize); > host->use_ecc =3D false; > =20 > if (nandc->props->qpic_v2) > @@ -2181,14 +2180,23 @@ static void qcom_nandc_codeword_fixup(struct qcom= _nand_host *host, int page) > static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, > int oob_required, int page) > { > + struct mtd_info *mtd =3D nand_to_mtd(chip); > struct qcom_nand_host *host =3D to_qcom_nand_host(chip); > struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); > + struct nand_ecc_ctrl *ecc =3D &chip->ecc; > u8 *data_buf, *oob_buf =3D NULL; > =20 > if (host->nr_boot_partitions) > qcom_nandc_codeword_fixup(host, page); > =20 > - nand_read_page_op(chip, page, 0, NULL, 0); > + nand_read_page_op(chip, page, 0, buf, mtd->writesize); > + nandc->buf_count =3D 0; > + nandc->buf_start =3D 0; > + host->use_ecc =3D true; > + clear_read_regs(nandc); > + set_address(host, 0, page); > + update_rw_regs(host, ecc->steps, true, 0); > + > data_buf =3D buf; > oob_buf =3D oob_required ? chip->oob_poi : NULL; > =20 > @@ -2258,6 +2266,9 @@ static int qcom_nandc_write_page(struct nand_chip *= chip, const uint8_t *buf, > =20 > nand_prog_page_begin_op(chip, page, 0, NULL, 0); > =20 > + set_address(host, 0, page); > + nandc->buf_count =3D 0; > + nandc->buf_start =3D 0; > clear_read_regs(nandc); > clear_bam_transaction(nandc); > =20 > @@ -3274,6 +3285,67 @@ static int qcom_param_page_type_exec(struct nand_c= hip *chip, const struct nand_ > return ret; > } > =20 > +static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct= nand_subop *subop) > +{ > + struct qcom_nand_host *host =3D to_qcom_nand_host(chip); > + struct qcom_nand_controller *nandc =3D get_qcom_nand_controller(chip); > + struct qcom_op q_op; > + int ret =3D 0; > + > + qcom_parse_instructions(chip, subop, &q_op); > + > + q_op.cmd_reg |=3D PAGE_ACC | LAST_PAGE; > + > + nandc->buf_count =3D 0; > + nandc->buf_start =3D 0; > + host->use_ecc =3D false; > + clear_read_regs(nandc); > + clear_bam_transaction(nandc); > + > + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg); > + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg); > + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg); > + nandc_set_reg(chip, NAND_DEV0_CFG0, > + host->cfg0_raw & ~(7 << CW_PER_PAGE)); > + nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); > + nandc_set_reg(chip, NAND_EXEC_CMD, 1); > + > + write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); > + write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); > + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); > + > + ret =3D submit_descs(nandc); > + if (ret) { > + dev_err(nandc->dev, "failure in sbumitting erase descriptor\n"); :) > + free_descs(nandc); > + goto err_out; > + } > + free_descs(nandc); > + > + ret =3D qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms); > + if (ret) > + goto err_out; > + > +err_out: > + return ret; > +} > + > +static int qcom_data_read_type_exec(struct nand_chip *chip, const struct= nand_subop *subop) > +{ > + /* currently read_exec_op() return 0 , and all the read operation handl= e in > + * actual API itself > + */ > + return 0; Mmmh, I don't think this is gonna work. I don't understand what you're doing here. What is "actual API itself"? What is "read_exec_op"? I doubt I am going to like what all this means. Please don't make any assumptions on what could come next. The core asks you to do something, just do it. If you can't then the parsing will fail. If the core has a fallback it's fine. If the core does not, we can discuss it. But please don't do any guesses like that, this is *exactly* why we introduced exec_op in the first place: you have access to the whole operation, so please handle it correctly. > +} > + > +static int qcom_data_write_type_exec(struct nand_chip *chip, const struc= t nand_subop *subop) > +{ > + /* currently write_exec_op() return 0, and all the write operation hand= le in > + * actual API itself > + */ > + return 0; > +} > + > static const struct nand_op_parser qcom_op_parser =3D NAND_OP_PARSER( > NAND_OP_PARSER_PATTERN( > qcom_misc_cmd_type_exec, > @@ -3294,6 +3366,23 @@ static const struct nand_op_parser qcom_op_parser = =3D NAND_OP_PARSER( > NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), > NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), > NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 512)), > + NAND_OP_PARSER_PATTERN( > + qcom_erase_cmd_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), > + NAND_OP_PARSER_PATTERN( > + qcom_data_read_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_ADDR_ELEM(false, MAX_ADDRESS_CYCLE), > + NAND_OP_PARSER_PAT_CMD_ELEM(false), > + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true), > + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 2048)), > + NAND_OP_PARSER_PATTERN( > + qcom_data_write_type_exec, > + NAND_OP_PARSER_PAT_CMD_ELEM(true), > + NAND_OP_PARSER_PAT_ADDR_ELEM(true, MAX_ADDRESS_CYCLE)), > ); > =20 > static int qcom_check_op(struct nand_chip *chip, Thanks, Miqu=C3=A8l From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4403C7EE23 for ; Thu, 8 Jun 2023 14:03:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q2MnoANFTIuskX77Di10DiHnRAxF+ajsuDOq0i7aTZI=; b=28Vylejc843Qoz oiD33e0imuuTjdBmeRJpyEIGjwLsebsK2f6geo+uTfVtcoA2EEDPUCplzwInmhgPTLVass6D6dv0M XAHHIxgH5j2FnkCX/605sufKgkztn/P5XDhcPfhSz17S1o8yK2J+G8RYKVuPC8LAJDBEqkkulVRnn t6TbW97QvQovar0qeqJH0/ZPqcDBzJJW3BshtUwgPMi+6qxZet+8NHUmKtpvpVBlaaS1Yd/DXPGmi 1Vyjh15LZXz8eA0D1i4om2zVE9PbbZFkvvStnlFAeW0h/INUcuqsUzTfWbbxYCreehNJLT4UigykW xn+yccW+q9YlxgtJJuMg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7GEI-009Yt8-1Y; Thu, 08 Jun 2023 14:03:10 +0000 Received: from relay4-d.mail.gandi.net ([217.70.183.196]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q7GEF-009YsB-0F for linux-mtd@lists.infradead.org; Thu, 08 Jun 2023 14:03:08 +0000 X-GND-Sasl: miquel.raynal@bootlin.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1686232984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jnCroNGp1M+uiCnGqikYI4/3yHPp7dCX3+gK/nsGdo4=; b=nqSOFk2jprLAEjTEnhpb8ceq1s4cTV5qOWx+88Y2Vn/72O7rPjsM4hheBZi0/JxbG2luyg i39tWsQkL99tlDnOl8UBMuN5Tn+sY1ttnPjaADKJkSJzuhwKC4vgvIFgoxzVQPpWzmFjoH tN4qpTrjTtUYJgSPikJ0EgOno80gRxufPNVQYs+/0Ilhb56T//Cf/FohEG7kcQSTySXuEn JbUX/K5a8FI6ezkCOu8yWI4W6t6PAj9Z9yeRorB2cJdNgIBuHkfHjCjrkkUG1PJaTXKw9m b/Gu0uwclxezU1Ttb5MlDumZcsdJsNl91v/kv9HQkbTQQTakL3n+iose5SSklg== X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 0396DE000B; Thu, 8 Jun 2023 14:03:03 +0000 (UTC) Date: Thu, 8 Jun 2023 16:03:03 +0200 From: Miquel Raynal To: Md Sadre Alam Cc: mani@kernel.org, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com Subject: Re: [PATCH v3 4/5] mtd: rawnand: qcom: Add support for read, write, erase exec_ops Message-ID: <20230608160303.51ea70a6@xps-13> In-Reply-To: <20230531124953.21007-4-quic_mdalam@quicinc.com> References: <20230531124953.21007-1-quic_mdalam@quicinc.com> <20230531124953.21007-4-quic_mdalam@quicinc.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230608_070307_376522_EEC00A13 X-CRM114-Status: GOOD ( 26.67 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgTWQsCgpxdWljX21kYWxhbUBxdWljaW5jLmNvbSB3cm90ZSBvbiBXZWQsIDMxIE1heSAyMDIz IDE4OjE5OjUyICswNTMwOgoKPiBUaGlzIGNoYW5nZSB3aWxsIGFkZCBleGVjX29wcyBzdXBwb3J0 IGZvciBSRUFELCBXUklURSwgYW5kIEVSQVNFCj4gY29tbWFuZC4KPiAKPiBDby1kZXZlbG9wZWQt Ynk6IFNyaWNoYXJhbiBSYW1hYmFkaHJhbiA8cXVpY19zcmljaGFyYUBxdWljaW5jLmNvbT4KPiBT aWduZWQtb2ZmLWJ5OiBTcmljaGFyYW4gUmFtYWJhZGhyYW4gPHF1aWNfc3JpY2hhcmFAcXVpY2lu Yy5jb20+Cj4gU2lnbmVkLW9mZi1ieTogTWQgU2FkcmUgQWxhbSA8cXVpY19tZGFsYW1AcXVpY2lu Yy5jb20+Cj4gLS0tCj4gQ2hhbmdlIGluIFt2M10KPiAKPiAqIFJlbW92ZWQgY2hpcC0+Y29udF9y ZWFkLm9uZ29pbmcgZmxhZy4KPiAKPiAqIFJlbW92ZWQgcHJlX2NvbW1hbmQgZnJvbSBlcmFzZV9l dHlwZV9leGVjX29wcy4KPiAKPiBDaGFuZ2UgaW4gW3YyXQo+IAo+ICogTWlzc2VkIHRvIHBvc3Qg Q292ZXItbGV0dGVyLCBzbyBwb3N0aW5nIHYyIHBhdGNoIHdpdGggY292ZXItbGV0dGVyLgo+IAo+ IENoYW5nZSBpbiBbdjFdCj4gCj4gKiBBZGRlZCBpbml0aWFsIHN1cHBvcnQgZm9yIGV4ZWNfb3Bz Lgo+IAo+ICBkcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMgfCA5NyArKysrKysrKysr KysrKysrKysrKysrKysrKysrKy0tCj4gIDEgZmlsZSBjaGFuZ2VkLCA5MyBpbnNlcnRpb25zKCsp LCA0IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL210ZC9uYW5kL3Jhdy9x Y29tX25hbmRjLmMgYi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRjLmMKPiBpbmRleCBi NDgyM2I3MmZlNzMuLjdkYzc2OWY5ZTc5NyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL210ZC9uYW5k L3Jhdy9xY29tX25hbmRjLmMKPiArKysgYi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9xY29tX25hbmRj LmMKPiBAQCAtMTU0Niw4ICsxNTQ2LDcgQEAgc3RhdGljIHZvaWQgcHJlX2NvbW1hbmQoc3RydWN0 IHFjb21fbmFuZF9ob3N0ICpob3N0LCBpbnQgY29tbWFuZCkKPiAgCj4gIAljbGVhcl9yZWFkX3Jl Z3MobmFuZGMpOwo+ICAKPiAtCWlmIChjb21tYW5kID09IE5BTkRfQ01EX0VSQVNFMSkKPiAtCQlj bGVhcl9iYW1fdHJhbnNhY3Rpb24obmFuZGMpOwo+ICsJY2xlYXJfYmFtX3RyYW5zYWN0aW9uKG5h bmRjKTsKPiAgfQo+ICAKPiAgLyoKPiBAQCAtMTc2NCw3ICsxNzYzLDcgQEAgcWNvbV9uYW5kY19y ZWFkX2N3X3JhdyhzdHJ1Y3QgbXRkX2luZm8gKm10ZCwgc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwK PiAgCWludCByZXQsIHJlZ19vZmYgPSBGTEFTSF9CVUZfQUNDLCByZWFkX2xvYyA9IDA7Cj4gIAlp bnQgcmF3X2N3ID0gY3c7Cj4gIAo+IC0JbmFuZF9yZWFkX3BhZ2Vfb3AoY2hpcCwgcGFnZSwgMCwg TlVMTCwgMCk7Cj4gKwluYW5kX3JlYWRfcGFnZV9vcChjaGlwLCBwYWdlLCAwLCBkYXRhX2J1Ziwg bXRkLT53cml0ZXNpemUpOwo+ICAJaG9zdC0+dXNlX2VjYyA9IGZhbHNlOwo+ICAKPiAgCWlmIChu YW5kYy0+cHJvcHMtPnFwaWNfdjIpCj4gQEAgLTIxODEsMTQgKzIxODAsMjMgQEAgc3RhdGljIHZv aWQgcWNvbV9uYW5kY19jb2Rld29yZF9maXh1cChzdHJ1Y3QgcWNvbV9uYW5kX2hvc3QgKmhvc3Qs IGludCBwYWdlKQo+ICBzdGF0aWMgaW50IHFjb21fbmFuZGNfcmVhZF9wYWdlKHN0cnVjdCBuYW5k X2NoaXAgKmNoaXAsIHVpbnQ4X3QgKmJ1ZiwKPiAgCQkJCWludCBvb2JfcmVxdWlyZWQsIGludCBw YWdlKQo+ICB7Cj4gKwlzdHJ1Y3QgbXRkX2luZm8gKm10ZCA9IG5hbmRfdG9fbXRkKGNoaXApOwo+ ICAJc3RydWN0IHFjb21fbmFuZF9ob3N0ICpob3N0ID0gdG9fcWNvbV9uYW5kX2hvc3QoY2hpcCk7 Cj4gIAlzdHJ1Y3QgcWNvbV9uYW5kX2NvbnRyb2xsZXIgKm5hbmRjID0gZ2V0X3Fjb21fbmFuZF9j b250cm9sbGVyKGNoaXApOwo+ICsJc3RydWN0IG5hbmRfZWNjX2N0cmwgKmVjYyA9ICZjaGlwLT5l Y2M7Cj4gIAl1OCAqZGF0YV9idWYsICpvb2JfYnVmID0gTlVMTDsKPiAgCj4gIAlpZiAoaG9zdC0+ bnJfYm9vdF9wYXJ0aXRpb25zKQo+ICAJCXFjb21fbmFuZGNfY29kZXdvcmRfZml4dXAoaG9zdCwg cGFnZSk7Cj4gIAo+IC0JbmFuZF9yZWFkX3BhZ2Vfb3AoY2hpcCwgcGFnZSwgMCwgTlVMTCwgMCk7 Cj4gKwluYW5kX3JlYWRfcGFnZV9vcChjaGlwLCBwYWdlLCAwLCBidWYsIG10ZC0+d3JpdGVzaXpl KTsKPiArCW5hbmRjLT5idWZfY291bnQgPSAwOwo+ICsJbmFuZGMtPmJ1Zl9zdGFydCA9IDA7Cj4g Kwlob3N0LT51c2VfZWNjID0gdHJ1ZTsKPiArCWNsZWFyX3JlYWRfcmVncyhuYW5kYyk7Cj4gKwlz ZXRfYWRkcmVzcyhob3N0LCAwLCBwYWdlKTsKPiArCXVwZGF0ZV9yd19yZWdzKGhvc3QsIGVjYy0+ c3RlcHMsIHRydWUsIDApOwo+ICsKPiAgCWRhdGFfYnVmID0gYnVmOwo+ICAJb29iX2J1ZiA9IG9v Yl9yZXF1aXJlZCA/IGNoaXAtPm9vYl9wb2kgOiBOVUxMOwo+ICAKPiBAQCAtMjI1OCw2ICsyMjY2 LDkgQEAgc3RhdGljIGludCBxY29tX25hbmRjX3dyaXRlX3BhZ2Uoc3RydWN0IG5hbmRfY2hpcCAq Y2hpcCwgY29uc3QgdWludDhfdCAqYnVmLAo+ICAKPiAgCW5hbmRfcHJvZ19wYWdlX2JlZ2luX29w KGNoaXAsIHBhZ2UsIDAsIE5VTEwsIDApOwo+ICAKPiArCXNldF9hZGRyZXNzKGhvc3QsIDAsIHBh Z2UpOwo+ICsJbmFuZGMtPmJ1Zl9jb3VudCA9IDA7Cj4gKwluYW5kYy0+YnVmX3N0YXJ0ID0gMDsK PiAgCWNsZWFyX3JlYWRfcmVncyhuYW5kYyk7Cj4gIAljbGVhcl9iYW1fdHJhbnNhY3Rpb24obmFu ZGMpOwo+ICAKPiBAQCAtMzI3NCw2ICszMjg1LDY3IEBAIHN0YXRpYyBpbnQgcWNvbV9wYXJhbV9w YWdlX3R5cGVfZXhlYyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCAgY29uc3Qgc3RydWN0IG5hbmRf Cj4gIAlyZXR1cm4gcmV0Owo+ICB9Cj4gIAo+ICtzdGF0aWMgaW50IHFjb21fZXJhc2VfY21kX3R5 cGVfZXhlYyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBjb25zdCBzdHJ1Y3QgbmFuZF9zdWJvcCAq c3Vib3ApCj4gK3sKPiArCXN0cnVjdCBxY29tX25hbmRfaG9zdCAqaG9zdCA9IHRvX3Fjb21fbmFu ZF9ob3N0KGNoaXApOwo+ICsJc3RydWN0IHFjb21fbmFuZF9jb250cm9sbGVyICpuYW5kYyA9IGdl dF9xY29tX25hbmRfY29udHJvbGxlcihjaGlwKTsKPiArCXN0cnVjdCBxY29tX29wIHFfb3A7Cj4g KwlpbnQgcmV0ID0gMDsKPiArCj4gKwlxY29tX3BhcnNlX2luc3RydWN0aW9ucyhjaGlwLCBzdWJv cCwgJnFfb3ApOwo+ICsKPiArCXFfb3AuY21kX3JlZyB8PSBQQUdFX0FDQyB8IExBU1RfUEFHRTsK PiArCj4gKwluYW5kYy0+YnVmX2NvdW50ID0gMDsKPiArCW5hbmRjLT5idWZfc3RhcnQgPSAwOwo+ ICsJaG9zdC0+dXNlX2VjYyA9IGZhbHNlOwo+ICsJY2xlYXJfcmVhZF9yZWdzKG5hbmRjKTsKPiAr CWNsZWFyX2JhbV90cmFuc2FjdGlvbihuYW5kYyk7Cj4gKwo+ICsJbmFuZGNfc2V0X3JlZyhjaGlw LCBOQU5EX0ZMQVNIX0NNRCwgcV9vcC5jbWRfcmVnKTsKPiArCW5hbmRjX3NldF9yZWcoY2hpcCwg TkFORF9BRERSMCwgcV9vcC5hZGRyMV9yZWcpOwo+ICsJbmFuZGNfc2V0X3JlZyhjaGlwLCBOQU5E X0FERFIxLCBxX29wLmFkZHIyX3JlZyk7Cj4gKwluYW5kY19zZXRfcmVnKGNoaXAsIE5BTkRfREVW MF9DRkcwLAo+ICsJCSAgICAgIGhvc3QtPmNmZzBfcmF3ICYgfig3IDw8IENXX1BFUl9QQUdFKSk7 Cj4gKwluYW5kY19zZXRfcmVnKGNoaXAsIE5BTkRfREVWMF9DRkcxLCBob3N0LT5jZmcxX3Jhdyk7 Cj4gKwluYW5kY19zZXRfcmVnKGNoaXAsIE5BTkRfRVhFQ19DTUQsIDEpOwo+ICsKPiArCXdyaXRl X3JlZ19kbWEobmFuZGMsIE5BTkRfRkxBU0hfQ01ELCAzLCBOQU5EX0JBTV9ORVhUX1NHTCk7Cj4g Kwl3cml0ZV9yZWdfZG1hKG5hbmRjLCBOQU5EX0RFVjBfQ0ZHMCwgMiwgTkFORF9CQU1fTkVYVF9T R0wpOwo+ICsJd3JpdGVfcmVnX2RtYShuYW5kYywgTkFORF9FWEVDX0NNRCwgMSwgTkFORF9CQU1f TkVYVF9TR0wpOwo+ICsKPiArCXJldCA9IHN1Ym1pdF9kZXNjcyhuYW5kYyk7Cj4gKwlpZiAocmV0 KSB7Cj4gKwkJZGV2X2VycihuYW5kYy0+ZGV2LCAiZmFpbHVyZSBpbiBzYnVtaXR0aW5nIGVyYXNl IGRlc2NyaXB0b3JcbiIpOwoKICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgOikKCj4gKwkJZnJlZV9kZXNjcyhuYW5kYyk7Cj4gKwkJZ290byBlcnJfb3V0Owo+ ICsJfQo+ICsJZnJlZV9kZXNjcyhuYW5kYyk7Cj4gKwo+ICsJcmV0ID0gcWNvbV93YWl0X3JkeV9w b2xsKGNoaXAsIHFfb3AucmR5X3RpbWVvdXRfbXMpOwo+ICsJaWYgKHJldCkKPiArCQlnb3RvIGVy cl9vdXQ7Cj4gKwo+ICtlcnJfb3V0Ogo+ICsJcmV0dXJuIHJldDsKPiArfQo+ICsKPiArc3RhdGlj IGludCBxY29tX2RhdGFfcmVhZF90eXBlX2V4ZWMoc3RydWN0IG5hbmRfY2hpcCAqY2hpcCwgY29u c3Qgc3RydWN0IG5hbmRfc3Vib3AgKnN1Ym9wKQo+ICt7Cj4gKwkvKiBjdXJyZW50bHkgcmVhZF9l eGVjX29wKCkgcmV0dXJuIDAgLCBhbmQgYWxsIHRoZSByZWFkIG9wZXJhdGlvbiBoYW5kbGUgaW4K PiArCSAqIGFjdHVhbCBBUEkgaXRzZWxmCj4gKwkgKi8KPiArCXJldHVybiAwOwoKTW1taCwgSSBk b24ndCB0aGluayB0aGlzIGlzIGdvbm5hIHdvcmsuIEkgZG9uJ3QgdW5kZXJzdGFuZCB3aGF0IHlv dSdyZQpkb2luZyBoZXJlLiBXaGF0IGlzICJhY3R1YWwgQVBJIGl0c2VsZiI/IFdoYXQgaXMgInJl YWRfZXhlY19vcCI/IEkKZG91YnQgSSBhbSBnb2luZyB0byBsaWtlIHdoYXQgYWxsIHRoaXMgbWVh bnMuIFBsZWFzZSBkb24ndCBtYWtlIGFueQphc3N1bXB0aW9ucyBvbiB3aGF0IGNvdWxkIGNvbWUg bmV4dC4gVGhlIGNvcmUgYXNrcyB5b3UgdG8gZG8gc29tZXRoaW5nLApqdXN0IGRvIGl0LiBJZiB5 b3UgY2FuJ3QgdGhlbiB0aGUgcGFyc2luZyB3aWxsIGZhaWwuIElmIHRoZSBjb3JlIGhhcyBhCmZh bGxiYWNrIGl0J3MgZmluZS4gSWYgdGhlIGNvcmUgZG9lcyBub3QsIHdlIGNhbiBkaXNjdXNzIGl0 LiBCdXQgcGxlYXNlCmRvbid0IGRvIGFueSBndWVzc2VzIGxpa2UgdGhhdCwgdGhpcyBpcyAqZXhh Y3RseSogd2h5IHdlIGludHJvZHVjZWQKZXhlY19vcCBpbiB0aGUgZmlyc3QgcGxhY2U6IHlvdSBo YXZlIGFjY2VzcyB0byB0aGUgd2hvbGUgb3BlcmF0aW9uLCBzbwpwbGVhc2UgaGFuZGxlIGl0IGNv cnJlY3RseS4KCj4gK30KPiArCj4gK3N0YXRpYyBpbnQgcWNvbV9kYXRhX3dyaXRlX3R5cGVfZXhl YyhzdHJ1Y3QgbmFuZF9jaGlwICpjaGlwLCBjb25zdCBzdHJ1Y3QgbmFuZF9zdWJvcCAqc3Vib3Ap Cj4gK3sKPiArCS8qIGN1cnJlbnRseSB3cml0ZV9leGVjX29wKCkgcmV0dXJuIDAsIGFuZCBhbGwg dGhlIHdyaXRlIG9wZXJhdGlvbiBoYW5kbGUgaW4KPiArCSAqIGFjdHVhbCBBUEkgaXRzZWxmCj4g KwkgKi8KPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICBzdGF0aWMgY29uc3Qgc3RydWN0IG5hbmRf b3BfcGFyc2VyIHFjb21fb3BfcGFyc2VyID0gTkFORF9PUF9QQVJTRVIoCj4gIAkJTkFORF9PUF9Q QVJTRVJfUEFUVEVSTigKPiAgCQkJcWNvbV9taXNjX2NtZF90eXBlX2V4ZWMsCj4gQEAgLTMyOTQs NiArMzM2NiwyMyBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IG5hbmRfb3BfcGFyc2VyIHFjb21fb3Bf cGFyc2VyID0gTkFORF9PUF9QQVJTRVIoCj4gIAkJCU5BTkRfT1BfUEFSU0VSX1BBVF9BRERSX0VM RU0oZmFsc2UsIE1BWF9BRERSRVNTX0NZQ0xFKSwKPiAgCQkJTkFORF9PUF9QQVJTRVJfUEFUX1dB SVRSRFlfRUxFTSh0cnVlKSwKPiAgCQkJTkFORF9PUF9QQVJTRVJfUEFUX0RBVEFfSU5fRUxFTShm YWxzZSwgNTEyKSksCj4gKwkJTkFORF9PUF9QQVJTRVJfUEFUVEVSTigKPiArCQkJcWNvbV9lcmFz ZV9jbWRfdHlwZV9leGVjLAo+ICsJCQlOQU5EX09QX1BBUlNFUl9QQVRfQ01EX0VMRU0oZmFsc2Up LAo+ICsJCQlOQU5EX09QX1BBUlNFUl9QQVRfQUREUl9FTEVNKGZhbHNlLCBNQVhfQUREUkVTU19D WUNMRSksCj4gKwkJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxFTShmYWxzZSksCj4gKwkJCU5B TkRfT1BfUEFSU0VSX1BBVF9XQUlUUkRZX0VMRU0oZmFsc2UpKSwKPiArCQlOQU5EX09QX1BBUlNF Ul9QQVRURVJOKAo+ICsJCQlxY29tX2RhdGFfcmVhZF90eXBlX2V4ZWMsCj4gKwkJCU5BTkRfT1Bf UEFSU0VSX1BBVF9DTURfRUxFTShmYWxzZSksCj4gKwkJCU5BTkRfT1BfUEFSU0VSX1BBVF9BRERS X0VMRU0oZmFsc2UsIE1BWF9BRERSRVNTX0NZQ0xFKSwKPiArCQkJTkFORF9PUF9QQVJTRVJfUEFU X0NNRF9FTEVNKGZhbHNlKSwKPiArCQkJTkFORF9PUF9QQVJTRVJfUEFUX1dBSVRSRFlfRUxFTSh0 cnVlKSwKPiArCQkJTkFORF9PUF9QQVJTRVJfUEFUX0RBVEFfSU5fRUxFTShmYWxzZSwgMjA0OCkp LAo+ICsJCU5BTkRfT1BfUEFSU0VSX1BBVFRFUk4oCj4gKwkJCXFjb21fZGF0YV93cml0ZV90eXBl X2V4ZWMsCj4gKwkJCU5BTkRfT1BfUEFSU0VSX1BBVF9DTURfRUxFTSh0cnVlKSwKPiArCQkJTkFO RF9PUF9QQVJTRVJfUEFUX0FERFJfRUxFTSh0cnVlLCBNQVhfQUREUkVTU19DWUNMRSkpLAo+ICAJ CSk7Cj4gIAo+ICBzdGF0aWMgaW50IHFjb21fY2hlY2tfb3Aoc3RydWN0IG5hbmRfY2hpcCAqY2hp cCwKCgpUaGFua3MsCk1pcXXDqGwKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpMaW51eCBNVEQgZGlzY3Vzc2lvbiBtYWlsaW5nIGxpc3QKaHR0 cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1tdGQvCg==