From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <bwidawsk@kernel.org>,
<dan.j.williams@intel.com>, <dave.jiang@intel.com>,
<linux-cxl@vger.kernel.org>, <rrichter@amd.com>,
<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map
Date: Thu, 22 Jun 2023 12:14:24 +0100 [thread overview]
Message-ID: <20230622121424.00004b46@Huawei.com> (raw)
In-Reply-To: <20230622035126.4130151-8-terry.bowman@amd.com>
On Wed, 21 Jun 2023 22:51:06 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> From: Robert Richter <rrichter@amd.com>
>
> The corresponding device of a register mapping is used for devm
> operations and logging. For operations with struct cxl_register_map
> the device needs to be kept track separately. To simpify the involved
> function interfaces, add @dev to cxl_register_map.
>
> While at it also reorder function arguments of cxl_map_device_regs()
> and cxl_map_component_regs() to have the object @cxl_register_map
> first.
>
> In a result a bunch of functions are available to be used with a
As a result? Not quite sure what this sentence means..
> @cxl_register_map object.
>
> This patch is in preparation of reworking the component register setup
> code.
>
> Signed-off-by: Robert Richter <rrichter@amd.com>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
I've no strong opinion on the reordering though I slightly prefer it as
you have it after this. Will let Dan comment on whether he likes that or not.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/hdm.c | 4 ++--
> drivers/cxl/core/regs.c | 18 ++++++++++++------
> drivers/cxl/cxl.h | 10 ++++++----
> drivers/cxl/pci.c | 23 +++++++++++------------
> 4 files changed, 31 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index 7889ff203a34..5abfa9276dac 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -85,6 +85,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> struct cxl_component_regs *regs)
> {
> struct cxl_register_map map = {
> + .dev = &port->dev,
> .resource = port->component_reg_phys,
> .base = crb,
> .max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> @@ -97,8 +98,7 @@ static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,
> return -ENODEV;
> }
>
> - return cxl_map_component_regs(&port->dev, regs, &map,
> - BIT(CXL_CM_CAP_CAP_ID_HDM));
> + return cxl_map_component_regs(&map, regs, BIT(CXL_CM_CAP_CAP_ID_HDM));
> }
>
> static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
> diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> index 6c4b33133918..713e4a9ca35a 100644
> --- a/drivers/cxl/core/regs.c
> +++ b/drivers/cxl/core/regs.c
> @@ -199,9 +199,11 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> return ret_val;
> }
>
> -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
> - struct cxl_register_map *map, unsigned long map_mask)
> +int cxl_map_component_regs(struct cxl_register_map *map,
> + struct cxl_component_regs *regs,
> + unsigned long map_mask)
> {
> + struct device *dev = map->dev;
> struct mapinfo {
> struct cxl_reg_map *rmap;
> void __iomem **addr;
> @@ -231,10 +233,10 @@ int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
> }
> EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
>
> -int cxl_map_device_regs(struct device *dev,
> - struct cxl_device_regs *regs,
> - struct cxl_register_map *map)
> +int cxl_map_device_regs(struct cxl_register_map *map,
> + struct cxl_device_regs *regs)
> {
> + struct device *dev = map->dev;
> resource_size_t phys_addr = map->resource;
> struct mapinfo {
> struct cxl_reg_map *rmap;
> @@ -302,7 +304,11 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> u32 regloc_size, regblocks;
> int regloc, i;
>
> - map->resource = CXL_RESOURCE_NONE;
> + *map = (struct cxl_register_map) {
> + .dev = &pdev->dev,
> + .resource = CXL_RESOURCE_NONE,
> + };
> +
> regloc = pci_find_dvsec_capability(pdev, PCI_DVSEC_VENDOR_ID_CXL,
> CXL_DVSEC_REG_LOCATOR);
> if (!regloc)
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 754cfe59ae37..bd68d5fabf21 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -231,6 +231,7 @@ struct cxl_device_reg_map {
>
> /**
> * struct cxl_register_map - DVSEC harvested register block mapping parameters
> + * @dev: device for devm operations and logging
> * @base: virtual base of the register-block-BAR + @block_offset
> * @resource: physical resource base of the register block
> * @max_size: maximum mapping size to perform register search
> @@ -239,6 +240,7 @@ struct cxl_device_reg_map {
> * @device_map: cxl_reg_maps for device registers
> */
> struct cxl_register_map {
> + struct device *dev;
> void __iomem *base;
> resource_size_t resource;
> resource_size_t max_size;
> @@ -253,11 +255,11 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
> struct cxl_component_reg_map *map);
> void cxl_probe_device_regs(struct device *dev, void __iomem *base,
> struct cxl_device_reg_map *map);
> -int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs,
> - struct cxl_register_map *map,
> +int cxl_map_component_regs(struct cxl_register_map *map,
> + struct cxl_component_regs *regs,
> unsigned long map_mask);
> -int cxl_map_device_regs(struct device *dev, struct cxl_device_regs *regs,
> - struct cxl_register_map *map);
> +int cxl_map_device_regs(struct cxl_register_map *map,
> + struct cxl_device_regs *regs);
>
> enum cxl_regloc_type;
> int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type,
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 0872f2233ed0..0a89b96e6a8d 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -274,9 +274,9 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
> return 0;
> }
>
> -static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
> +static int cxl_map_regblock(struct cxl_register_map *map)
> {
> - struct device *dev = &pdev->dev;
> + struct device *dev = map->dev;
>
> map->base = ioremap(map->resource, map->max_size);
> if (!map->base) {
> @@ -288,18 +288,17 @@ static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
> return 0;
> }
>
> -static void cxl_unmap_regblock(struct pci_dev *pdev,
> - struct cxl_register_map *map)
> +static void cxl_unmap_regblock(struct cxl_register_map *map)
> {
> iounmap(map->base);
> map->base = NULL;
> }
>
> -static int cxl_probe_regs(struct pci_dev *pdev, struct cxl_register_map *map)
> +static int cxl_probe_regs(struct cxl_register_map *map)
> {
> struct cxl_component_reg_map *comp_map;
> struct cxl_device_reg_map *dev_map;
> - struct device *dev = &pdev->dev;
> + struct device *dev = map->dev;
> void __iomem *base = map->base;
>
> switch (map->reg_type) {
> @@ -346,12 +345,12 @@ static int cxl_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
> if (rc)
> return rc;
>
> - rc = cxl_map_regblock(pdev, map);
> + rc = cxl_map_regblock(map);
> if (rc)
> return rc;
>
> - rc = cxl_probe_regs(pdev, map);
> - cxl_unmap_regblock(pdev, map);
> + rc = cxl_probe_regs(map);
> + cxl_unmap_regblock(map);
>
> return rc;
> }
> @@ -688,7 +687,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> if (rc)
> return rc;
>
> - rc = cxl_map_device_regs(&pdev->dev, &cxlds->regs.device_regs, &map);
> + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs);
> if (rc)
> return rc;
>
> @@ -703,8 +702,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>
> cxlds->component_reg_phys = map.resource;
>
> - rc = cxl_map_component_regs(&pdev->dev, &cxlds->regs.component,
> - &map, BIT(CXL_CM_CAP_CAP_ID_RAS));
> + rc = cxl_map_component_regs(&map, &cxlds->regs.component,
> + BIT(CXL_CM_CAP_CAP_ID_RAS));
> if (rc)
> dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");
>
next prev parent reply other threads:[~2023-06-22 11:14 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 3:50 [PATCH v6 00/27] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-06-22 3:51 ` [PATCH v6 01/27] cxl/port: Fix NULL pointer access in devm_cxl_add_port() Terry Bowman
2023-06-22 7:17 ` Robert Richter
2023-06-22 3:51 ` [PATCH v6 02/27] cxl/acpi: Probe RCRB later during RCH downstream port creation Terry Bowman
2023-06-22 22:36 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 03/27] cxl: Updates for CXL Test to work with RCH Terry Bowman
2023-06-22 9:53 ` Jonathan Cameron
2023-06-22 10:03 ` Robert Richter
2023-06-22 14:02 ` Terry Bowman
2023-06-22 22:38 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 04/27] cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability Terry Bowman
2023-06-22 22:51 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 05/27] cxl: Rename member @dport of struct cxl_dport to @dport_dev Terry Bowman
2023-06-22 9:54 ` Jonathan Cameron
2023-06-22 22:53 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 06/27] cxl: Rename 'uport' to 'uport_dev' Terry Bowman
2023-06-22 9:56 ` Jonathan Cameron
2023-06-22 22:54 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 07/27] cxl/core/regs: Add @dev to cxl_register_map Terry Bowman
2023-06-22 11:14 ` Jonathan Cameron [this message]
2023-06-22 23:07 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 08/27] cxl/pci: Refactor component register discovery for reuse Terry Bowman
2023-06-22 23:14 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 09/27] cxl/acpi: Move add_host_bridge_uport() after cxl_get_chbs() Terry Bowman
2023-06-22 23:17 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 10/27] cxl/acpi: Directly bind the CEDT detected CHBCR to the Host Bridge's port Terry Bowman
2023-06-22 23:28 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 11/27] cxl/port: Remove Component Register base address from struct cxl_dport Terry Bowman
2023-06-22 23:47 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup Terry Bowman
2023-06-22 23:48 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 13/27] cxl/mem: Prepare for early RCH dport component register setup Terry Bowman
2023-06-22 11:17 ` Jonathan Cameron
2023-06-22 23:50 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 14/27] cxl/pci: Early setup RCH dport component registers from RCRB Terry Bowman
2023-06-22 23:58 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 15/27] cxl/port: Store the port's Component Register mappings in struct cxl_port Terry Bowman
2023-06-22 13:20 ` Jonathan Cameron
2023-06-23 0:00 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 16/27] cxl/port: Store the downstream port's Component Register mappings in struct cxl_dport Terry Bowman
2023-06-23 0:01 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 17/27] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-06-23 0:02 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 18/27] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-06-23 0:03 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 19/27] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-06-23 0:04 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 20/27] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-06-22 13:17 ` Jonathan Cameron
2023-06-23 0:10 ` Dave Jiang
2023-06-22 3:51 ` [PATCH v6 21/27] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-06-22 3:51 ` [PATCH v6 22/27] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-06-22 3:51 ` [PATCH v6 23/27] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-06-22 13:16 ` Jonathan Cameron
2023-06-22 14:42 ` Terry Bowman
2023-06-22 3:51 ` [PATCH v6 24/27] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-06-22 3:51 ` [PATCH v6 25/27] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-06-22 13:12 ` Jonathan Cameron
2023-06-22 16:33 ` Terry Bowman
2023-06-23 13:28 ` Jonathan Cameron
2023-06-22 3:51 ` [PATCH v6 26/27] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-06-22 3:51 ` Terry Bowman
2023-06-22 3:51 ` [PATCH v6 27/27] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-06-22 13:07 ` Jonathan Cameron
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