From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Subject: Re: [PATCH v2 04/12] cxl: Remove leftover attribute documentation in 'struct cxl_dev_state'
Date: Thu, 22 Jun 2023 14:50:39 +0100 [thread overview]
Message-ID: <20230622145039.00004e43@Huawei.com> (raw)
In-Reply-To: <a4292abc-1884-5d39-4802-1e06b54328d8@intel.com>
On Thu, 15 Jun 2023 14:29:08 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> On 6/14/23 18:29, Dan Williams wrote:
> > commit 14d788740774 ("cxl/mem: Consolidate CXL DVSEC Range enumeration
> > in the core")
> >
> > ...removed @info from 'struct cxl_dev_state', but neglected to remove
> > the corresponding kernel-doc entry. Complete the removal.
> >
> > Reported-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
> > Closes: http://lore.kernel.org/r/20230606121054.000069e1@Huawei.com
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> > ---
> > drivers/cxl/cxlmem.h | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> > index 8e4ba5b52902..66896fc6c43f 100644
> > --- a/drivers/cxl/cxlmem.h
> > +++ b/drivers/cxl/cxlmem.h
> > @@ -287,7 +287,6 @@ struct cxl_poison_state {
> > * @next_volatile_bytes: volatile capacity change pending device reset
> > * @next_persistent_bytes: persistent capacity change pending device reset
> > * @component_reg_phys: register base of component registers
> > - * @info: Cached DVSEC information about the device.
> > * @serial: PCIe Device Serial Number
> > * @event: event log driver state
> > * @poison: poison driver state info
> >
next prev parent reply other threads:[~2023-06-22 13:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 1:29 [PATCH v2 00/12] Device memory prep Dan Williams
2023-06-15 1:29 ` [PATCH v2 01/12] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-15 1:29 ` [PATCH v2 02/12] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-15 1:29 ` [PATCH v2 03/12] cxl: Fix kernel-doc warnings Dan Williams
2023-06-15 21:28 ` Dave Jiang
2023-06-22 13:50 ` Jonathan Cameron
2023-06-15 1:29 ` [PATCH v2 04/12] cxl: Remove leftover attribute documentation in 'struct cxl_dev_state' Dan Williams
2023-06-15 21:29 ` Dave Jiang
2023-06-22 13:50 ` Jonathan Cameron [this message]
2023-06-15 1:30 ` [PATCH v2 05/12] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-15 1:30 ` [PATCH v2 06/12] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-15 21:30 ` Dave Jiang
2023-06-22 13:52 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 07/12] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM} Dan Williams
2023-06-15 21:31 ` Dave Jiang
2023-06-15 1:30 ` [PATCH v2 08/12] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-15 21:32 ` Dave Jiang
2023-06-15 1:30 ` [PATCH v2 09/12] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-15 1:30 ` [PATCH v2 10/12] cxl/pci: Unconditionally unmask 256B Flit errors Dan Williams
2023-06-15 21:34 ` Dave Jiang
2023-06-22 13:55 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 11/12] cxl/port: Enumerate cxl link capabilities Dan Williams
2023-06-15 21:37 ` Dave Jiang
2023-06-16 0:07 ` Dan Williams
2023-06-16 19:16 ` Dan Williams
2023-06-22 14:04 ` Jonathan Cameron
2023-06-15 1:30 ` [PATCH v2 12/12] cxl/memdev: Formalize endpoint port linkage Dan Williams
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