From: Ani Sinha <anisinha@redhat.com>
To: qemu-devel@nongnu.org, Thomas Huth <thuth@redhat.com>,
Laurent Vivier <lvivier@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: Ani Sinha <anisinha@redhat.com>,
mst@redhat.com, imammedo@redhat.com,
Michael Labiuk <michael.labiuk@virtuozzo.com>
Subject: [RESEND PATCH v5 4/5] tests/qtest/hd-geo-test: fix incorrect pcie-root-port usage and simplify test
Date: Mon, 26 Jun 2023 21:42:43 +0530 [thread overview]
Message-ID: <20230626161244.4145-5-anisinha@redhat.com> (raw)
In-Reply-To: <20230626161244.4145-1-anisinha@redhat.com>
The test attaches a SCSI controller to a non-zero slot and a pcie-to-pci bridge
on slot 0 on the same pcie-root-port. Since a downstream device can be attached
to a pcie-root-port only on slot 0, the above test configuration is not allowed.
Additionally using pcie.0 as id for pcie-root-port is incorrect as that id is
reserved only for the root bus.
In the test scenario, there is no need to attach a pcie-root-port to the
root complex. A SCSI controller can be attached to a pcie-to-pci bridge
which can then be directly attached to the root bus (pcie.0).
Fix the test and simplify it.
CC: mst@redhat.com
CC: imammedo@redhat.com
CC: Michael Labiuk <michael.labiuk@virtuozzo.com>
Signed-off-by: Ani Sinha <anisinha@redhat.com>
---
tests/qtest/hd-geo-test.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/tests/qtest/hd-geo-test.c b/tests/qtest/hd-geo-test.c
index 5aa258a2b3..d08bffad91 100644
--- a/tests/qtest/hd-geo-test.c
+++ b/tests/qtest/hd-geo-test.c
@@ -784,14 +784,12 @@ static void test_override_scsi(void)
test_override(args, "pc", expected);
}
-static void setup_pci_bridge(TestArgs *args, const char *id, const char *rootid)
+static void setup_pci_bridge(TestArgs *args, const char *id)
{
- char *root, *br;
- root = g_strdup_printf("-device pcie-root-port,id=%s", rootid);
- br = g_strdup_printf("-device pcie-pci-bridge,bus=%s,id=%s", rootid, id);
+ char *br;
+ br = g_strdup_printf("-device pcie-pci-bridge,bus=pcie.0,id=%s", id);
- args->argc = append_arg(args->argc, args->argv, ARGV_SIZE, root);
args->argc = append_arg(args->argc, args->argv, ARGV_SIZE, br);
}
@@ -811,8 +809,8 @@ static void test_override_scsi_q35(void)
add_drive_with_mbr(args, empty_mbr, 1);
add_drive_with_mbr(args, empty_mbr, 1);
add_drive_with_mbr(args, empty_mbr, 1);
- setup_pci_bridge(args, "pcie.0", "br");
- add_scsi_controller(args, "lsi53c895a", "br", 3);
+ setup_pci_bridge(args, "pcie-pci-br");
+ add_scsi_controller(args, "lsi53c895a", "pcie-pci-br", 3);
add_scsi_disk(args, 0, 0, 0, 0, 0, 10000, 120, 30);
add_scsi_disk(args, 1, 0, 0, 1, 0, 9000, 120, 30);
add_scsi_disk(args, 2, 0, 0, 2, 0, 1, 0, 0);
@@ -868,9 +866,9 @@ static void test_override_virtio_blk_q35(void)
};
add_drive_with_mbr(args, empty_mbr, 1);
add_drive_with_mbr(args, empty_mbr, 1);
- setup_pci_bridge(args, "pcie.0", "br");
- add_virtio_disk(args, 0, "br", 3, 10000, 120, 30);
- add_virtio_disk(args, 1, "br", 4, 9000, 120, 30);
+ setup_pci_bridge(args, "pcie-pci-br");
+ add_virtio_disk(args, 0, "pcie-pci-br", 3, 10000, 120, 30);
+ add_virtio_disk(args, 1, "pcie-pci-br", 4, 9000, 120, 30);
test_override(args, "q35", expected);
}
--
2.39.1
next prev parent reply other threads:[~2023-06-26 16:16 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 16:12 [RESEND PATCH v5 0/5] test and QEMU fixes to ensure proper PCIE device usage Ani Sinha
2023-06-26 16:12 ` [RESEND PATCH v5 1/5] tests/acpi: allow changes in DSDT.noacpihp table blob Ani Sinha
2023-06-26 16:12 ` [RESEND PATCH v5 2/5] tests/acpi/bios-tables-test: use the correct slot on the pcie-root-port Ani Sinha
2023-06-26 16:12 ` [RESEND PATCH v5 3/5] tests/acpi/bios-tables-test: update acpi blob q35/DSDT.noacpihp Ani Sinha
2023-06-26 16:12 ` Ani Sinha [this message]
2023-06-27 8:54 ` [RESEND PATCH v5 4/5] tests/qtest/hd-geo-test: fix incorrect pcie-root-port usage and simplify test Igor Mammedov
2023-06-27 9:26 ` Ani Sinha
2023-06-26 16:12 ` [RESEND PATCH v5 5/5] hw/pci: ensure PCIE devices are plugged into only slot 0 of PCIE port Ani Sinha
2023-06-27 9:02 ` Igor Mammedov
2023-06-27 9:53 ` Ani Sinha
2023-06-27 11:55 ` Michael S. Tsirkin
2023-06-27 12:01 ` Ani Sinha
2023-06-27 12:06 ` Michael S. Tsirkin
2023-06-27 11:55 ` Ani Sinha
2023-06-27 11:58 ` Igor Mammedov
2023-06-27 12:23 ` Michael S. Tsirkin
2023-06-27 12:29 ` Ani Sinha
2023-06-27 14:23 ` Michael S. Tsirkin
2023-06-27 12:38 ` Igor Mammedov
2023-06-27 14:27 ` Michael S. Tsirkin
2023-06-28 15:02 ` Ani Sinha
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