From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5B9BC0015E for ; Tue, 4 Jul 2023 15:18:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=b+LhAEuPauFXyNDtQhTyGHDonBZKhzrgutSETJfFD9U=; b=iJlEme7Oo1G4j+ E9FQjHKlsiEqefRMLhvXy29Gu4j+WgSueADb/CN4XAogW+x6kX0Mu0rMPGjqusm+g6VAdKTHI7s3O F2VOJt3JqvLRcUd1WzxiCHCE9Oox4TSaHHXikKJQGm5m3iuGUU/FZMSHtSTLBPMrFKA+//LKxFytH jfqldN45gjP5ldvbA9k8jT9Ul6MoyStolcPiMJvQvuWvshaV8PLMGVwYGLQrN4/fZCyLjtfcuJGXb 7iqsOutq8Iqf0Btk7c+kxn2S4BD5MoLaEGcG8SFonSN2WJTXvivzZF3mZ2WmlSjnUSXcmv6khESq9 CfvP7iuPB99Tp7LHfwag==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qGhnn-00DdaW-1D; Tue, 04 Jul 2023 15:18:51 +0000 Received: from relay1-d.mail.gandi.net ([217.70.183.193]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qGhnj-00DdYq-1R for linux-mtd@lists.infradead.org; Tue, 04 Jul 2023 15:18:49 +0000 X-GND-Sasl: miquel.raynal@bootlin.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1688483920; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OOvkfol+in6TlFekwc6yFBfYV4hihVZfvdrg+oeWEiY=; b=fuoeTIaHM53J4Bi7m2dpkM3y/mKzgeEGAk93wTuSL4DYZBF3IVUoDBQid1s6kWvHgkdl9Y vWmuCiD+pdV/lpY1ypI/M+BlhfFoSXKrsqD/EcMM/9NWAjwIdVjt1UYbxlUREMGJwkUhEk jTv1zJXMEytp1Q9gpyss6KkThWksLHl7JfHSrus2KGFTzhhtVaw9MZKD5VxE4f/UQVuXS6 FVZTjkXdZIpAj4VzYJW8tGSTN5G2Mg6bozCbmolEMspZRI+FOAXjhTsmtjTi/g/QsRMM1I MvWwx6zEqqLmTVL2kAYDpnLyI+wcpMxqQCo00veg5dMeF7Wzr6p3s2aEskrLZQ== X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 33B5B240006; Tue, 4 Jul 2023 15:18:38 +0000 (UTC) Date: Tue, 4 Jul 2023 17:18:37 +0200 From: Miquel Raynal To: William Zhang Cc: Broadcom Kernel List , Linux MTD List , f.fainelli@gmail.com, rafal@milecki.pl, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, computersforpeace@gmail.com, anand.gore@broadcom.com, dregan@mail.com, kamal.dasu@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, Florian Fainelli , Rob Herring , linux-kernel@vger.kernel.org, Vignesh Raghavendra , Richard Weinberger , Boris Brezillon , Kamal Dasu Subject: Re: [PATCH v3 1/5] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller Message-ID: <20230704171837.3db54fb8@xps-13> In-Reply-To: <20230627193738.19596-2-william.zhang@broadcom.com> References: <20230627193738.19596-1-william.zhang@broadcom.com> <20230627193738.19596-2-william.zhang@broadcom.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230704_081847_773845_1DBFA3CE X-CRM114-Status: GOOD ( 21.79 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org SGkgV2lsbGlhbSwKCndpbGxpYW0uemhhbmdAYnJvYWRjb20uY29tIHdyb3RlIG9uIFR1ZSwgMjcg SnVuIDIwMjMgMTI6Mzc6MzQgLTA3MDA6Cgo+IHY3LjIgY29udHJvbGxlciBoYXMgZGlmZmVyZW50 IEVDQyBsZXZlbCBmaWVsZCBzaXplIGFuZCBzaGlmdCBpbiB0aGUgYWNjCj4gY29udHJvbCByZWdp c3RlciB0aGFuIGl0cyBwcmVkZWNlc3NvciBhbmQgc3VjY2Vzc29yIGNvbnRyb2xsZXIuIEl0IG5l ZWRzCj4gdG8gYmUgc2V0IHNwZWNpZmljYWxseS4KPiAKPiBGaXhlczogZGVjYmE2ZDQ3ODY5ICgi bXRkOiBicmNtbmFuZDogQWRkIHY3LjIgY29udHJvbGxlciBzdXBwb3J0IikKPiBTaWduZWQtb2Zm LWJ5OiBXaWxsaWFtIFpoYW5nIDx3aWxsaWFtLnpoYW5nQGJyb2FkY29tLmNvbT4KPiBSZXZpZXdl ZC1ieTogRmxvcmlhbiBGYWluZWxsaSA8Zmxvcmlhbi5mYWluZWxsaUBicm9hZGNvbS5jb20+Cj4g Cj4gLS0tCj4gCj4gQ2hhbmdlcyBpbiB2MzogTm9uZQo+IENoYW5nZXMgaW4gdjI6Cj4gLSBVc2Ug ZHJpdmVyIHN0YXRpYyBkYXRhIGZvciBFQ0MgbGV2ZWwgc2hpZnQKPiAKPiAgZHJpdmVycy9tdGQv bmFuZC9yYXcvYnJjbW5hbmQvYnJjbW5hbmQuYyB8IDc0ICsrKysrKysrKysrKystLS0tLS0tLS0t LQo+ICAxIGZpbGUgY2hhbmdlZCwgNDEgaW5zZXJ0aW9ucygrKSwgMzMgZGVsZXRpb25zKC0pCj4g Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbXRkL25hbmQvcmF3L2JyY21uYW5kL2JyY21uYW5kLmMg Yi9kcml2ZXJzL210ZC9uYW5kL3Jhdy9icmNtbmFuZC9icmNtbmFuZC5jCj4gaW5kZXggMmU5YzJl MmQ5YzlmLi42OTcwOTQxOTUxNmEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9tdGQvbmFuZC9yYXcv YnJjbW5hbmQvYnJjbW5hbmQuYwo+ICsrKyBiL2RyaXZlcnMvbXRkL25hbmQvcmF3L2JyY21uYW5k L2JyY21uYW5kLmMKPiBAQCAtMjcyLDYgKzI3Miw3IEBAIHN0cnVjdCBicmNtbmFuZF9jb250cm9s bGVyIHsKPiAgCWNvbnN0IHVuc2lnbmVkIGludAkqcGFnZV9zaXplczsKPiAgCXVuc2lnbmVkIGlu dAkJcGFnZV9zaXplX3NoaWZ0Owo+ICAJdW5zaWduZWQgaW50CQltYXhfb29iOwo+ICsJdTMyCQkJ ZWNjX2xldmVsX3NoaWZ0Owo+ICAJdTMyCQkJZmVhdHVyZXM7Cj4gIAo+ICAJLyogZm9yIGxvdy1w b3dlciBzdGFuZGJ5L3Jlc3VtZSBvbmx5ICovCj4gQEAgLTU5Niw2ICs1OTcsMzQgQEAgZW51bSB7 Cj4gIAlJTlRGQ19DVExSX1JFQURZCQk9IEJJVCgzMSksCj4gIH07Cj4gIAo+ICsvKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioKPiArICogTkFORCBBQ0MgQ09OVFJPTCBiaXRmaWVsZAo+ICsgKgo+ICsgKiBTb21lIGJp dHMgaGF2ZSByZW1haW5lZCBjb25zdGFudCB0aHJvdWdob3V0IGhhcmR3YXJlIHJldmlzaW9uLCB3 aGlsZQo+ICsgKiBvdGhlcnMgaGF2ZSBzaGlmdGVkIGFyb3VuZC4KPiArICoqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq Lwo+ICsKPiArLyogQ29uc3RhbnQgZm9yIGFsbCB2ZXJzaW9ucyAod2hlcmUgc3VwcG9ydGVkKSAq Lwo+ICtlbnVtIHsKPiArCS8qIFNlZSBCUkNNTkFORF9IQVNfQ0FDSEVfTU9ERSAqLwo+ICsJQUND X0NPTlRST0xfQ0FDSEVfTU9ERQkJCQk9IEJJVCgyMiksCj4gKwo+ICsJLyogU2VlIEJSQ01OQU5E X0hBU19QUkVGRVRDSCAqLwo+ICsJQUNDX0NPTlRST0xfUFJFRkVUQ0gJCQkJPSBCSVQoMjMpLAo+ ICsKPiArCUFDQ19DT05UUk9MX1BBR0VfSElUCQkJCT0gQklUKDI0KSwKPiArCUFDQ19DT05UUk9M X1dSX1BSRUVNUFQJCQkJPSBCSVQoMjUpLAo+ICsJQUNDX0NPTlRST0xfUEFSVElBTF9QQUdFCQkJ PSBCSVQoMjYpLAo+ICsJQUNDX0NPTlRST0xfUkRfRVJBU0VECQkJCT0gQklUKDI3KSwKPiArCUFD Q19DT05UUk9MX0ZBU1RfUEdNX1JESU4JCQk9IEJJVCgyOCksCj4gKwlBQ0NfQ09OVFJPTF9XUl9F Q0MJCQkJPSBCSVQoMzApLAo+ICsJQUNDX0NPTlRST0xfUkRfRUNDCQkJCT0gQklUKDMxKSwKPiAr Cj4gKwlBQ0NfQ09OVFJPTF9FQ0NfU0hJRlQJCQkJPSAxNiwKPiArCS8qIE9ubHkgZm9yIHY3LjIg Ki8KPiArCUFDQ19DT05UUk9MX0VDQ19FWFRfU0hJRlQJCQk9IDEzLAo+ICt9OwoKVGhlc2UgZG8g bm90IGxvb2sgbGlrZSB0aGV5IGZpdCB0aGUgcHVycG9zZSBvZiBlbnVtcy4gQXQgbGVhc3Qga2Vl cAp0aGVzZSB0d28gbGFzdCBkZWZpbml0aW9ucyBvdXRzaWRlIGxpa2UgYmVmb3JlICh5b3UgY2Fu IHJlbmFtZSB0aGVtLCBJCmRvbid0IG1pbmQpLgoKTEdUTSBvdGhlcndpc2UuCgo+ICsKPiAgc3Rh dGljIGlubGluZSBib29sIGJyY21uYW5kX25vbl9tbWlvX29wcyhzdHJ1Y3QgYnJjbW5hbmRfY29u dHJvbGxlciAqY3RybCkKPiAgewo+ICAjaWYgSVNfRU5BQkxFRChDT05GSUdfTVREX05BTkRfQlJD TU5BTkRfQkNNQSkKPiBAQCAtNzM3LDYgKzc2NiwxMiBAQCBzdGF0aWMgaW50IGJyY21uYW5kX3Jl dmlzaW9uX2luaXQoc3RydWN0IGJyY21uYW5kX2NvbnRyb2xsZXIgKmN0cmwpCj4gIAllbHNlIGlm IChvZl9wcm9wZXJ0eV9yZWFkX2Jvb2woY3RybC0+ZGV2LT5vZl9ub2RlLCAiYnJjbSxuYW5kLWhh cy13cCIpKQo+ICAJCWN0cmwtPmZlYXR1cmVzIHw9IEJSQ01OQU5EX0hBU19XUDsKPiAgCj4gKwkv KiB2Ny4yIGhhcyBkaWZmZXJlbnQgZWNjIGxldmVsIHNoaWZ0IGluIHRoZSBhY2MgcmVnaXN0ZXIg Ki8KPiArCWlmIChjdHJsLT5uYW5kX3ZlcnNpb24gPT0gMHgwNzAyKQo+ICsJCWN0cmwtPmVjY19s ZXZlbF9zaGlmdCA9IEFDQ19DT05UUk9MX0VDQ19FWFRfU0hJRlQ7Cj4gKwllbHNlCj4gKwkJY3Ry bC0+ZWNjX2xldmVsX3NoaWZ0ID0gQUNDX0NPTlRST0xfRUNDX1NISUZUOwo+ICsKPiAgCXJldHVy biAwOwo+ICB9Cj4gIAo+IEBAIC05MzEsMzAgKzk2Niw2IEBAIHN0YXRpYyBpbmxpbmUgaW50IGJy Y21uYW5kX2NtZF9zaGlmdChzdHJ1Y3QgYnJjbW5hbmRfY29udHJvbGxlciAqY3RybCkKPiAgCXJl dHVybiAwOwo+ICB9Cj4gIAo+IC0vKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioKPiAtICogTkFORCBBQ0MgQ09OVFJP TCBiaXRmaWVsZAo+IC0gKgo+IC0gKiBTb21lIGJpdHMgaGF2ZSByZW1haW5lZCBjb25zdGFudCB0 aHJvdWdob3V0IGhhcmR3YXJlIHJldmlzaW9uLCB3aGlsZQo+IC0gKiBvdGhlcnMgaGF2ZSBzaGlm dGVkIGFyb3VuZC4KPiAtICoqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioqKioq KioqKioqKioqKioqKioqKioqKioqKioqKioqKioqLwo+IC0KPiAtLyogQ29uc3RhbnQgZm9yIGFs bCB2ZXJzaW9ucyAod2hlcmUgc3VwcG9ydGVkKSAqLwo+IC1lbnVtIHsKPiAtCS8qIFNlZSBCUkNN TkFORF9IQVNfQ0FDSEVfTU9ERSAqLwo+IC0JQUNDX0NPTlRST0xfQ0FDSEVfTU9ERQkJCQk9IEJJ VCgyMiksCj4gLQo+IC0JLyogU2VlIEJSQ01OQU5EX0hBU19QUkVGRVRDSCAqLwo+IC0JQUNDX0NP TlRST0xfUFJFRkVUQ0gJCQkJPSBCSVQoMjMpLAo+IC0KPiAtCUFDQ19DT05UUk9MX1BBR0VfSElU CQkJCT0gQklUKDI0KSwKPiAtCUFDQ19DT05UUk9MX1dSX1BSRUVNUFQJCQkJPSBCSVQoMjUpLAo+ IC0JQUNDX0NPTlRST0xfUEFSVElBTF9QQUdFCQkJPSBCSVQoMjYpLAo+IC0JQUNDX0NPTlRST0xf UkRfRVJBU0VECQkJCT0gQklUKDI3KSwKPiAtCUFDQ19DT05UUk9MX0ZBU1RfUEdNX1JESU4JCQk9 IEJJVCgyOCksCj4gLQlBQ0NfQ09OVFJPTF9XUl9FQ0MJCQkJPSBCSVQoMzApLAo+IC0JQUNDX0NP TlRST0xfUkRfRUNDCQkJCT0gQklUKDMxKSwKPiAtfTsKPiAtCj4gIHN0YXRpYyBpbmxpbmUgdTMy IGJyY21uYW5kX3NwYXJlX2FyZWFfbWFzayhzdHJ1Y3QgYnJjbW5hbmRfY29udHJvbGxlciAqY3Ry bCkKPiAgewo+ICAJaWYgKGN0cmwtPm5hbmRfdmVyc2lvbiA9PSAweDA3MDIpCj4gQEAgLTk2Nywx OCArOTc4LDE1IEBAIHN0YXRpYyBpbmxpbmUgdTMyIGJyY21uYW5kX3NwYXJlX2FyZWFfbWFzayhz dHJ1Y3QgYnJjbW5hbmRfY29udHJvbGxlciAqY3RybCkKPiAgCQlyZXR1cm4gR0VOTUFTSyg0LCAw KTsKPiAgfQo+ICAKPiAtI2RlZmluZSBOQU5EX0FDQ19DT05UUk9MX0VDQ19TSElGVAkxNgo+IC0j ZGVmaW5lIE5BTkRfQUNDX0NPTlRST0xfRUNDX0VYVF9TSElGVAkxMwo+IC0KPiAgc3RhdGljIGlu bGluZSB1MzIgYnJjbW5hbmRfZWNjX2xldmVsX21hc2soc3RydWN0IGJyY21uYW5kX2NvbnRyb2xs ZXIgKmN0cmwpCj4gIHsKPiAgCXUzMiBtYXNrID0gKGN0cmwtPm5hbmRfdmVyc2lvbiA+PSAweDA2 MDApID8gMHgxZiA6IDB4MGY7Cj4gIAo+IC0JbWFzayA8PD0gTkFORF9BQ0NfQ09OVFJPTF9FQ0Nf U0hJRlQ7Cj4gKwltYXNrIDw8PSBBQ0NfQ09OVFJPTF9FQ0NfU0hJRlQ7Cj4gIAo+ICAJLyogdjcu MiBpbmNsdWRlcyBhZGRpdGlvbmFsIEVDQyBsZXZlbHMgKi8KPiAtCWlmIChjdHJsLT5uYW5kX3Zl cnNpb24gPj0gMHgwNzAyKQo+IC0JCW1hc2sgfD0gMHg3IDw8IE5BTkRfQUNDX0NPTlRST0xfRUND X0VYVF9TSElGVDsKPiArCWlmIChjdHJsLT5uYW5kX3ZlcnNpb24gPT0gMHgwNzAyKQo+ICsJCW1h c2sgfD0gMHg3IDw8IEFDQ19DT05UUk9MX0VDQ19FWFRfU0hJRlQ7Cj4gIAo+ICAJcmV0dXJuIG1h c2s7Cj4gIH0KPiBAQCAtOTkyLDggKzEwMDAsOCBAQCBzdGF0aWMgdm9pZCBicmNtbmFuZF9zZXRf ZWNjX2VuYWJsZWQoc3RydWN0IGJyY21uYW5kX2hvc3QgKmhvc3QsIGludCBlbikKPiAgCj4gIAlp ZiAoZW4pIHsKPiAgCQlhY2NfY29udHJvbCB8PSBlY2NfZmxhZ3M7IC8qIGVuYWJsZSBSRC9XUiBF Q0MgKi8KPiAtCQlhY2NfY29udHJvbCB8PSBob3N0LT5od2NmZy5lY2NfbGV2ZWwKPiAtCQkJICAg ICAgIDw8IE5BTkRfQUNDX0NPTlRST0xfRUNDX1NISUZUOwo+ICsJCWFjY19jb250cm9sICY9IH5i cmNtbmFuZF9lY2NfbGV2ZWxfbWFzayhjdHJsKTsKPiArCQlhY2NfY29udHJvbCB8PSBob3N0LT5o d2NmZy5lY2NfbGV2ZWwgPDwgY3RybC0+ZWNjX2xldmVsX3NoaWZ0Owo+ICAJfSBlbHNlIHsKPiAg CQlhY2NfY29udHJvbCAmPSB+ZWNjX2ZsYWdzOyAvKiBkaXNhYmxlIFJEL1dSIEVDQyAqLwo+ICAJ CWFjY19jb250cm9sICY9IH5icmNtbmFuZF9lY2NfbGV2ZWxfbWFzayhjdHJsKTsKPiBAQCAtMjU2 MSw3ICsyNTY5LDcgQEAgc3RhdGljIGludCBicmNtbmFuZF9zZXRfY2ZnKHN0cnVjdCBicmNtbmFu ZF9ob3N0ICpob3N0LAo+ICAJdG1wICY9IH5icmNtbmFuZF9lY2NfbGV2ZWxfbWFzayhjdHJsKTsK PiAgCXRtcCAmPSB+YnJjbW5hbmRfc3BhcmVfYXJlYV9tYXNrKGN0cmwpOwo+ICAJaWYgKGN0cmwt Pm5hbmRfdmVyc2lvbiA+PSAweDAzMDIpIHsKPiAtCQl0bXAgfD0gY2ZnLT5lY2NfbGV2ZWwgPDwg TkFORF9BQ0NfQ09OVFJPTF9FQ0NfU0hJRlQ7Cj4gKwkJdG1wIHw9IGNmZy0+ZWNjX2xldmVsIDw8 IGN0cmwtPmVjY19sZXZlbF9zaGlmdDsKPiAgCQl0bXAgfD0gY2ZnLT5zcGFyZV9hcmVhX3NpemU7 Cj4gIAl9Cj4gIAluYW5kX3dyaXRlcmVnKGN0cmwsIGFjY19jb250cm9sX29mZnMsIHRtcCk7CgoK VGhhbmtzLApNaXF1w6hsCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KTGludXggTVREIGRpc2N1c3Npb24gbWFpbGluZyBsaXN0Cmh0dHA6Ly9s aXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtbXRkLwo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00963EB64D9 for ; Tue, 4 Jul 2023 15:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231770AbjGDPTA (ORCPT ); Tue, 4 Jul 2023 11:19:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231230AbjGDPSm (ORCPT ); Tue, 4 Jul 2023 11:18:42 -0400 Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B312BD for ; Tue, 4 Jul 2023 08:18:41 -0700 (PDT) X-GND-Sasl: miquel.raynal@bootlin.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1688483920; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OOvkfol+in6TlFekwc6yFBfYV4hihVZfvdrg+oeWEiY=; b=fuoeTIaHM53J4Bi7m2dpkM3y/mKzgeEGAk93wTuSL4DYZBF3IVUoDBQid1s6kWvHgkdl9Y vWmuCiD+pdV/lpY1ypI/M+BlhfFoSXKrsqD/EcMM/9NWAjwIdVjt1UYbxlUREMGJwkUhEk jTv1zJXMEytp1Q9gpyss6KkThWksLHl7JfHSrus2KGFTzhhtVaw9MZKD5VxE4f/UQVuXS6 FVZTjkXdZIpAj4VzYJW8tGSTN5G2Mg6bozCbmolEMspZRI+FOAXjhTsmtjTi/g/QsRMM1I MvWwx6zEqqLmTVL2kAYDpnLyI+wcpMxqQCo00veg5dMeF7Wzr6p3s2aEskrLZQ== X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com X-GND-Sasl: miquel.raynal@bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 33B5B240006; Tue, 4 Jul 2023 15:18:38 +0000 (UTC) Date: Tue, 4 Jul 2023 17:18:37 +0200 From: Miquel Raynal To: William Zhang Cc: Broadcom Kernel List , Linux MTD List , f.fainelli@gmail.com, rafal@milecki.pl, kursad.oney@broadcom.com, joel.peshkin@broadcom.com, computersforpeace@gmail.com, anand.gore@broadcom.com, dregan@mail.com, kamal.dasu@broadcom.com, tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, Florian Fainelli , Rob Herring , linux-kernel@vger.kernel.org, Vignesh Raghavendra , Richard Weinberger , Boris Brezillon , Kamal Dasu Subject: Re: [PATCH v3 1/5] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller Message-ID: <20230704171837.3db54fb8@xps-13> In-Reply-To: <20230627193738.19596-2-william.zhang@broadcom.com> References: <20230627193738.19596-1-william.zhang@broadcom.com> <20230627193738.19596-2-william.zhang@broadcom.com> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi William, william.zhang@broadcom.com wrote on Tue, 27 Jun 2023 12:37:34 -0700: > v7.2 controller has different ECC level field size and shift in the acc > control register than its predecessor and successor controller. It needs > to be set specifically. >=20 > Fixes: decba6d47869 ("mtd: brcmnand: Add v7.2 controller support") > Signed-off-by: William Zhang > Reviewed-by: Florian Fainelli >=20 > --- >=20 > Changes in v3: None > Changes in v2: > - Use driver static data for ECC level shift >=20 > drivers/mtd/nand/raw/brcmnand/brcmnand.c | 74 +++++++++++++----------- > 1 file changed, 41 insertions(+), 33 deletions(-) >=20 > diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/= raw/brcmnand/brcmnand.c > index 2e9c2e2d9c9f..69709419516a 100644 > --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c > +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c > @@ -272,6 +272,7 @@ struct brcmnand_controller { > const unsigned int *page_sizes; > unsigned int page_size_shift; > unsigned int max_oob; > + u32 ecc_level_shift; > u32 features; > =20 > /* for low-power standby/resume only */ > @@ -596,6 +597,34 @@ enum { > INTFC_CTLR_READY =3D BIT(31), > }; > =20 > +/*********************************************************************** > + * NAND ACC CONTROL bitfield > + * > + * Some bits have remained constant throughout hardware revision, while > + * others have shifted around. > + ***********************************************************************/ > + > +/* Constant for all versions (where supported) */ > +enum { > + /* See BRCMNAND_HAS_CACHE_MODE */ > + ACC_CONTROL_CACHE_MODE =3D BIT(22), > + > + /* See BRCMNAND_HAS_PREFETCH */ > + ACC_CONTROL_PREFETCH =3D BIT(23), > + > + ACC_CONTROL_PAGE_HIT =3D BIT(24), > + ACC_CONTROL_WR_PREEMPT =3D BIT(25), > + ACC_CONTROL_PARTIAL_PAGE =3D BIT(26), > + ACC_CONTROL_RD_ERASED =3D BIT(27), > + ACC_CONTROL_FAST_PGM_RDIN =3D BIT(28), > + ACC_CONTROL_WR_ECC =3D BIT(30), > + ACC_CONTROL_RD_ECC =3D BIT(31), > + > + ACC_CONTROL_ECC_SHIFT =3D 16, > + /* Only for v7.2 */ > + ACC_CONTROL_ECC_EXT_SHIFT =3D 13, > +}; These do not look like they fit the purpose of enums. At least keep these two last definitions outside like before (you can rename them, I don't mind). LGTM otherwise. > + > static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctr= l) > { > #if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA) > @@ -737,6 +766,12 @@ static int brcmnand_revision_init(struct brcmnand_co= ntroller *ctrl) > else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) > ctrl->features |=3D BRCMNAND_HAS_WP; > =20 > + /* v7.2 has different ecc level shift in the acc register */ > + if (ctrl->nand_version =3D=3D 0x0702) > + ctrl->ecc_level_shift =3D ACC_CONTROL_ECC_EXT_SHIFT; > + else > + ctrl->ecc_level_shift =3D ACC_CONTROL_ECC_SHIFT; > + > return 0; > } > =20 > @@ -931,30 +966,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand= _controller *ctrl) > return 0; > } > =20 > -/*********************************************************************** > - * NAND ACC CONTROL bitfield > - * > - * Some bits have remained constant throughout hardware revision, while > - * others have shifted around. > - ***********************************************************************/ > - > -/* Constant for all versions (where supported) */ > -enum { > - /* See BRCMNAND_HAS_CACHE_MODE */ > - ACC_CONTROL_CACHE_MODE =3D BIT(22), > - > - /* See BRCMNAND_HAS_PREFETCH */ > - ACC_CONTROL_PREFETCH =3D BIT(23), > - > - ACC_CONTROL_PAGE_HIT =3D BIT(24), > - ACC_CONTROL_WR_PREEMPT =3D BIT(25), > - ACC_CONTROL_PARTIAL_PAGE =3D BIT(26), > - ACC_CONTROL_RD_ERASED =3D BIT(27), > - ACC_CONTROL_FAST_PGM_RDIN =3D BIT(28), > - ACC_CONTROL_WR_ECC =3D BIT(30), > - ACC_CONTROL_RD_ECC =3D BIT(31), > -}; > - > static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *c= trl) > { > if (ctrl->nand_version =3D=3D 0x0702) > @@ -967,18 +978,15 @@ static inline u32 brcmnand_spare_area_mask(struct b= rcmnand_controller *ctrl) > return GENMASK(4, 0); > } > =20 > -#define NAND_ACC_CONTROL_ECC_SHIFT 16 > -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 > - > static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ct= rl) > { > u32 mask =3D (ctrl->nand_version >=3D 0x0600) ? 0x1f : 0x0f; > =20 > - mask <<=3D NAND_ACC_CONTROL_ECC_SHIFT; > + mask <<=3D ACC_CONTROL_ECC_SHIFT; > =20 > /* v7.2 includes additional ECC levels */ > - if (ctrl->nand_version >=3D 0x0702) > - mask |=3D 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; > + if (ctrl->nand_version =3D=3D 0x0702) > + mask |=3D 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; > =20 > return mask; > } > @@ -992,8 +1000,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand= _host *host, int en) > =20 > if (en) { > acc_control |=3D ecc_flags; /* enable RD/WR ECC */ > - acc_control |=3D host->hwcfg.ecc_level > - << NAND_ACC_CONTROL_ECC_SHIFT; > + acc_control &=3D ~brcmnand_ecc_level_mask(ctrl); > + acc_control |=3D host->hwcfg.ecc_level << ctrl->ecc_level_shift; > } else { > acc_control &=3D ~ecc_flags; /* disable RD/WR ECC */ > acc_control &=3D ~brcmnand_ecc_level_mask(ctrl); > @@ -2561,7 +2569,7 @@ static int brcmnand_set_cfg(struct brcmnand_host *h= ost, > tmp &=3D ~brcmnand_ecc_level_mask(ctrl); > tmp &=3D ~brcmnand_spare_area_mask(ctrl); > if (ctrl->nand_version >=3D 0x0302) { > - tmp |=3D cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; > + tmp |=3D cfg->ecc_level << ctrl->ecc_level_shift; > tmp |=3D cfg->spare_area_size; > } > nand_writereg(ctrl, acc_control_offs, tmp); Thanks, Miqu=C3=A8l