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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id w6-20020a17090633c600b0098748422178sm14079846eja.56.2023.07.05.01.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jul 2023 01:14:54 -0700 (PDT) Date: Wed, 5 Jul 2023 10:14:53 +0200 From: Andrew Jones To: Yong-Xuan Wang Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com Subject: Re: [PATCH v4 0/6] Add RISC-V KVM AIA Support Message-ID: <20230705-31abcb5d920f105c9a9ccaa8@orel> References: <20230621145500.25624-1-yongxuan.wang@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230621145500.25624-1-yongxuan.wang@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Wed, Jun 21, 2023 at 02:54:50PM +0000, Yong-Xuan Wang wrote: > This series adds support for KVM AIA in RISC-V architecture. > > In order to test these patches, we require Linux with KVM AIA support which can > be found in the riscv_kvm_aia_hwaccel_v1 branch at > https://github.com/avpatel/linux.git Is it possible to add irqfd support? Maybe even as simply as the diff below? If not, can you explain what still needs to be done in order to do so? Thanks, drew diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 00fdb60fc6ab..b38d9bb5506a 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -371,6 +371,7 @@ static void riscv_imsic_realize(DeviceState *dev, Error **errp) } msi_nonbroken = true; + kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); } static Property riscv_imsic_properties[] = {