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From: Stefan Eichenberger <eichest@gmail.com>
To: netdev@vger.kernel.org, andrew@lunn.ch, hkallweit1@gmail.com,
	linux@armlinux.org.uk, francesco.dolcini@toradex.com
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, eichest@gmail.com
Subject: [PATCH net-next v2 2/4] net: phy: add registers to support 1000BASE-T1
Date: Mon, 10 Jul 2023 22:58:58 +0200	[thread overview]
Message-ID: <20230710205900.52894-3-eichest@gmail.com> (raw)
In-Reply-To: <20230710205900.52894-1-eichest@gmail.com>

Add registers and definitions to support 1000BASE-T1. This includes the
PCS Control and Status registers (3.2304 and 3.2305) as well as some
missing bits on the PMA/PMD extended ability register (1.18) and PMA/PMD
CTRL (1.2100) register.

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
---
 include/uapi/linux/mdio.h | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h
index b826598d1e94c..ffa821cb291a5 100644
--- a/include/uapi/linux/mdio.h
+++ b/include/uapi/linux/mdio.h
@@ -82,6 +82,8 @@
 #define MDIO_AN_10BT1_AN_CTRL	526	/* 10BASE-T1 AN control register */
 #define MDIO_AN_10BT1_AN_STAT	527	/* 10BASE-T1 AN status register */
 #define MDIO_PMA_PMD_BT1_CTRL	2100	/* BASE-T1 PMA/PMD control register */
+#define MDIO_PCS_1000BT1_CTRL	2304	/* 1000BASE-T1 PCS control register */
+#define MDIO_PCS_1000BT1_STAT	2305	/* 1000BASE-T1 PCS status register */
 
 /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
 #define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
@@ -332,6 +334,7 @@
 #define MDIO_PCS_10T1L_CTRL_RESET	0x8000	/* PCS reset */
 
 /* BASE-T1 PMA/PMD extended ability register. */
+#define MDIO_PMA_PMD_BT1_B1000_ABLE	0x0002	/* 1000BASE-T1 Ability */
 #define MDIO_PMA_PMD_BT1_B10L_ABLE	0x0004	/* 10BASE-T1L Ability */
 
 /* BASE-T1 auto-negotiation advertisement register [15:0] */
@@ -373,7 +376,14 @@
 #define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L	0x4000 /* 10BASE-T1L LP EEE ability advertisement */
 
 /* BASE-T1 PMA/PMD control register */
-#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST	0x4000 /* MASTER-SLAVE config value */
+#define MDIO_PMA_PMD_BT1_CTRL_STRAP		0x000F /* Type selection (Strap) */
+#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000	0x0001 /* Select 1000BASE-T1 */
+#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST		0x4000 /* MASTER-SLAVE config value */
+
+/* 1000BASE-T1 PCS control register */
+#define MDIO_PCS_1000BT1_LOW_POWER	0x0800 /* Low power mode */
+#define MDIO_PCS_1000BT1_DISABLE_TX	0x4000 /* Global PMA transmit disable */
+#define MDIO_PCS_1000BT1_CTRL_RESET	0x8000 /* Software reset value */
 
 /* EEE Supported/Advertisement/LP Advertisement registers.
  *
-- 
2.39.2


  parent reply	other threads:[~2023-07-10 20:59 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-10 20:58 [PATCH net-next v2 0/4] Add a driver for the Marvell 88Q2110 PHY Stefan Eichenberger
2023-07-10 20:58 ` [PATCH net-next v2 1/4] net: phy: add the link modes for 1000BASE-T1 Ethernet PHY Stefan Eichenberger
2023-07-10 21:10   ` Andrew Lunn
2023-07-13 14:10     ` Stefan Eichenberger
2023-07-13 15:18       ` Andrew Lunn
2023-07-14  3:51         ` Stefan Eichenberger
2023-07-14  4:05           ` Andrew Lunn
2023-07-10 20:58 ` Stefan Eichenberger [this message]
2023-07-10 20:58 ` [PATCH net-next v2 3/4] net: phy: c45: add support for 1000BASE-T1 Stefan Eichenberger
2023-07-10 21:14   ` Francesco Dolcini
2023-07-10 20:59 ` [PATCH net-next v2 4/4] net: phy: marvell-88q2xxx: add driver for the Marvell 88Q2110 PHY Stefan Eichenberger
2023-07-10 21:20   ` Andrew Lunn
2023-07-13  9:42     ` Stefan Eichenberger
2023-07-13 10:14       ` Russell King (Oracle)
2023-07-13 11:41         ` Stefan Eichenberger
2023-07-10 21:26   ` Francesco Dolcini
2023-07-10 21:40   ` Andrew Lunn
2023-07-13  7:00   ` Russell King (Oracle)

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