From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C24253DE for ; Mon, 17 Jul 2023 15:59:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8F28C433C8; Mon, 17 Jul 2023 15:59:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689609572; bh=mmNtx5DaCDSRpy/BMCSXBwbmRPuUIz4XFGeGgtAykCg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bcN+QDhTGO43S68G//SgxaH9wKR50gFXFbSk0rjCodtNU4hMLKoXmJhAycajkEXCU olADYw/g75sw6tM0wGiOQwUcMD5jsLdkNP+TAclWpDPQsAQfhUgzw7OcIVVm/odLfF uBYlGvZ6T9f9OhFVeCfhwwVpxC4ENk3506WGw66iy8eFCK8jY19gKzkAfZMieh2RWw GPSbuI9t7JyCC9dtdHulnvO4qqr8WmO9HhiFMCcp+qPuguiXw4fwEc4AOCtq/cQmHk yWSIiQiclE7hX4yLNzrEIOXfdkIK9olTBOp+fRxPA/kbsx3cHhA/c2ZXDy7fB7MDTA oaBYmzU9z2cpQ== Date: Mon, 17 Jul 2023 21:29:10 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Minghuan Lian , Mingkai Hu , Roy Zang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev Subject: Re: [PATCH 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Message-ID: <20230717155910.GB35455@thinkpad> References: <20230615164113.2270698-1-Frank.Li@nxp.com> <20230615164113.2270698-2-Frank.Li@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230615164113.2270698-2-Frank.Li@nxp.com> On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote: > From: Xiaowei Bao > > A workaround for the issue where the PCI Express Endpoint (EP) controller > loses the values of the Maximum Link Width and Supported Link Speed from > the Link Capabilities Register, which initially configured by the Reset > Configuration Word (RCW) during a link-down or hot reset event. > If this fixes an issue, then there should be a Fixes tag. > Signed-off-by: Xiaowei Bao > Signed-off-by: Hou Zhiqiang > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index 4e4fdd1dfea7..2ef02d827eeb 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -45,6 +45,7 @@ struct ls_pcie_ep { > struct pci_epc_features *ls_epc; > const struct ls_pcie_ep_drvdata *drvdata; > int irq; > + u32 lnkcap; > bool big_endian; > }; > > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > struct ls_pcie_ep *pcie = dev_id; > struct dw_pcie *pci = pcie->pci; > u32 val, cfg; > + u8 offset; > > val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); > ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > return IRQ_NONE; > > if (val & PEX_PF0_PME_MES_DR_LUD) { > + Please add a comment on why the LNKCAP is being restored here. > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + > + dw_pcie_dbi_ro_wr_en(pci); > + dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); lnkcap is a 32-bit variable, so you should use dw_pcie_writel_dbi(). - Mani > + dw_pcie_dbi_ro_wr_dis(pci); > + > cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); > cfg |= PEX_PF0_CFG_READY; > ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > struct ls_pcie_ep *pcie; > struct pci_epc_features *ls_epc; > struct resource *dbi_base; > + u8 offset; > int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, pcie); > > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > + > ret = dw_pcie_ep_init(&pci->ep); > if (ret) > return ret; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D44FEB64DC for ; Mon, 17 Jul 2023 21:59:22 +0000 (UTC) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Tue, 18 Jul 2023 01:59:34 +1000 (AEST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BAE1D61130; Mon, 17 Jul 2023 15:59:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8F28C433C8; Mon, 17 Jul 2023 15:59:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689609572; bh=mmNtx5DaCDSRpy/BMCSXBwbmRPuUIz4XFGeGgtAykCg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bcN+QDhTGO43S68G//SgxaH9wKR50gFXFbSk0rjCodtNU4hMLKoXmJhAycajkEXCU olADYw/g75sw6tM0wGiOQwUcMD5jsLdkNP+TAclWpDPQsAQfhUgzw7OcIVVm/odLfF uBYlGvZ6T9f9OhFVeCfhwwVpxC4ENk3506WGw66iy8eFCK8jY19gKzkAfZMieh2RWw GPSbuI9t7JyCC9dtdHulnvO4qqr8WmO9HhiFMCcp+qPuguiXw4fwEc4AOCtq/cQmHk yWSIiQiclE7hX4yLNzrEIOXfdkIK9olTBOp+fRxPA/kbsx3cHhA/c2ZXDy7fB7MDTA oaBYmzU9z2cpQ== Date: Mon, 17 Jul 2023 21:29:10 +0530 From: Manivannan Sadhasivam To: Frank Li Subject: Re: [PATCH 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Message-ID: <20230717155910.GB35455@thinkpad> References: <20230615164113.2270698-1-Frank.Li@nxp.com> <20230615164113.2270698-2-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230615164113.2270698-2-Frank.Li@nxp.com> X-Mailman-Approved-At: Tue, 18 Jul 2023 07:55:09 +1000 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , imx@lists.linux.dev, Rob Herring , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Lorenzo Pieralisi , open list , Minghuan Lian , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Roy Zang , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , Mingkai Hu Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Jun 15, 2023 at 12:41:12PM -0400, Frank Li wrote: > From: Xiaowei Bao > > A workaround for the issue where the PCI Express Endpoint (EP) controller > loses the values of the Maximum Link Width and Supported Link Speed from > the Link Capabilities Register, which initially configured by the Reset > Configuration Word (RCW) during a link-down or hot reset event. > If this fixes an issue, then there should be a Fixes tag. > Signed-off-by: Xiaowei Bao > Signed-off-by: Hou Zhiqiang > Signed-off-by: Frank Li > --- > drivers/pci/controller/dwc/pci-layerscape-ep.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c > index 4e4fdd1dfea7..2ef02d827eeb 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c > @@ -45,6 +45,7 @@ struct ls_pcie_ep { > struct pci_epc_features *ls_epc; > const struct ls_pcie_ep_drvdata *drvdata; > int irq; > + u32 lnkcap; > bool big_endian; > }; > > @@ -73,6 +74,7 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > struct ls_pcie_ep *pcie = dev_id; > struct dw_pcie *pci = pcie->pci; > u32 val, cfg; > + u8 offset; > > val = ls_lut_readl(pcie, PEX_PF0_PME_MES_DR); > ls_lut_writel(pcie, PEX_PF0_PME_MES_DR, val); > @@ -81,6 +83,13 @@ static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id) > return IRQ_NONE; > > if (val & PEX_PF0_PME_MES_DR_LUD) { > + Please add a comment on why the LNKCAP is being restored here. > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + > + dw_pcie_dbi_ro_wr_en(pci); > + dw_pcie_writew_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap); lnkcap is a 32-bit variable, so you should use dw_pcie_writel_dbi(). - Mani > + dw_pcie_dbi_ro_wr_dis(pci); > + > cfg = ls_lut_readl(pcie, PEX_PF0_CONFIG); > cfg |= PEX_PF0_CFG_READY; > ls_lut_writel(pcie, PEX_PF0_CONFIG, cfg); > @@ -216,6 +225,7 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > struct ls_pcie_ep *pcie; > struct pci_epc_features *ls_epc; > struct resource *dbi_base; > + u8 offset; > int ret; > > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > @@ -252,6 +262,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev) > > platform_set_drvdata(pdev, pcie); > > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > + > ret = dw_pcie_ep_init(&pci->ep); > if (ret) > return ret; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qLQdJ-004U6H-0m for linux-arm-kernel@lists.infradead.org; Mon, 17 Jul 2023 15:59:34 +0000 Date: Mon, 17 Jul 2023 21:29:10 +0530 From: Manivannan Sadhasivam Subject: Re: [PATCH 2/2] PCI: layerscape: Add the workaround for lost link capablities during reset Message-ID: <20230717155910.GB35455@thinkpad> References: <20230615164113.2270698-1-Frank.Li@nxp.com> <20230615164113.2270698-2-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230615164113.2270698-2-Frank.Li@nxp.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+lwn-linux-arm-kernel=archive.lwn.net@lists.infradead.org List-Archive: To: Frank Li Cc: Minghuan Lian , Mingkai Hu , Roy Zang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "open list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , "moderated list:PCI DRIVER FOR FREESCALE LAYERSCAPE" , open list , imx@lists.linux.dev T24gVGh1LCBKdW4gMTUsIDIwMjMgYXQgMTI6NDE6MTJQTSAtMDQwMCwgRnJhbmsgTGkgd3JvdGU6 Cj4gRnJvbTogWGlhb3dlaSBCYW8gPHhpYW93ZWkuYmFvQG54cC5jb20+Cj4gCj4gQSB3b3JrYXJv dW5kIGZvciB0aGUgaXNzdWUgd2hlcmUgdGhlIFBDSSBFeHByZXNzIEVuZHBvaW50IChFUCkgY29u dHJvbGxlcgo+IGxvc2VzIHRoZSB2YWx1ZXMgb2YgdGhlIE1heGltdW0gTGluayBXaWR0aCBhbmQg U3VwcG9ydGVkIExpbmsgU3BlZWQgZnJvbQo+IHRoZSBMaW5rIENhcGFiaWxpdGllcyBSZWdpc3Rl ciwgd2hpY2ggaW5pdGlhbGx5IGNvbmZpZ3VyZWQgYnkgdGhlIFJlc2V0Cj4gQ29uZmlndXJhdGlv biBXb3JkIChSQ1cpIGR1cmluZyBhIGxpbmstZG93biBvciBob3QgcmVzZXQgZXZlbnQuCj4gCgpJ ZiB0aGlzIGZpeGVzIGFuIGlzc3VlLCB0aGVuIHRoZXJlIHNob3VsZCBiZSBhIEZpeGVzIHRhZy4K Cj4gU2lnbmVkLW9mZi1ieTogWGlhb3dlaSBCYW8gPHhpYW93ZWkuYmFvQG54cC5jb20+Cj4gU2ln bmVkLW9mZi1ieTogSG91IFpoaXFpYW5nIDxaaGlxaWFuZy5Ib3VAbnhwLmNvbT4KPiBTaWduZWQt b2ZmLWJ5OiBGcmFuayBMaSA8RnJhbmsuTGlAbnhwLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9wY2kv Y29udHJvbGxlci9kd2MvcGNpLWxheWVyc2NhcGUtZXAuYyB8IDEzICsrKysrKysrKysrKysKPiAg MSBmaWxlIGNoYW5nZWQsIDEzIGluc2VydGlvbnMoKykKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVy cy9wY2kvY29udHJvbGxlci9kd2MvcGNpLWxheWVyc2NhcGUtZXAuYyBiL2RyaXZlcnMvcGNpL2Nv bnRyb2xsZXIvZHdjL3BjaS1sYXllcnNjYXBlLWVwLmMKPiBpbmRleCA0ZTRmZGQxZGZlYTcuLjJl ZjAyZDgyN2VlYiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2kt bGF5ZXJzY2FwZS1lcC5jCj4gKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpLWxh eWVyc2NhcGUtZXAuYwo+IEBAIC00NSw2ICs0NSw3IEBAIHN0cnVjdCBsc19wY2llX2VwIHsKPiAg CXN0cnVjdCBwY2lfZXBjX2ZlYXR1cmVzCQkqbHNfZXBjOwo+ICAJY29uc3Qgc3RydWN0IGxzX3Bj aWVfZXBfZHJ2ZGF0YSAqZHJ2ZGF0YTsKPiAgCWludAkJCQlpcnE7Cj4gKwl1MzIJCQkJbG5rY2Fw Owo+ICAJYm9vbAkJCQliaWdfZW5kaWFuOwo+ICB9Owo+ICAKPiBAQCAtNzMsNiArNzQsNyBAQCBz dGF0aWMgaXJxcmV0dXJuX3QgbHNfcGNpZV9lcF9ldmVudF9oYW5kbGVyKGludCBpcnEsIHZvaWQg KmRldl9pZCkKPiAgCXN0cnVjdCBsc19wY2llX2VwICpwY2llID0gZGV2X2lkOwo+ICAJc3RydWN0 IGR3X3BjaWUgKnBjaSA9IHBjaWUtPnBjaTsKPiAgCXUzMiB2YWwsIGNmZzsKPiArCXU4IG9mZnNl dDsKPiAgCj4gIAl2YWwgPSBsc19sdXRfcmVhZGwocGNpZSwgUEVYX1BGMF9QTUVfTUVTX0RSKTsK PiAgCWxzX2x1dF93cml0ZWwocGNpZSwgUEVYX1BGMF9QTUVfTUVTX0RSLCB2YWwpOwo+IEBAIC04 MSw2ICs4MywxMyBAQCBzdGF0aWMgaXJxcmV0dXJuX3QgbHNfcGNpZV9lcF9ldmVudF9oYW5kbGVy KGludCBpcnEsIHZvaWQgKmRldl9pZCkKPiAgCQlyZXR1cm4gSVJRX05PTkU7Cj4gIAo+ICAJaWYg KHZhbCAmIFBFWF9QRjBfUE1FX01FU19EUl9MVUQpIHsKPiArCgpQbGVhc2UgYWRkIGEgY29tbWVu dCBvbiB3aHkgdGhlIExOS0NBUCBpcyBiZWluZyByZXN0b3JlZCBoZXJlLgoKPiArCQlvZmZzZXQg PSBkd19wY2llX2ZpbmRfY2FwYWJpbGl0eShwY2ksIFBDSV9DQVBfSURfRVhQKTsKPiArCj4gKwkJ ZHdfcGNpZV9kYmlfcm9fd3JfZW4ocGNpKTsKPiArCQlkd19wY2llX3dyaXRld19kYmkocGNpLCBv ZmZzZXQgKyBQQ0lfRVhQX0xOS0NBUCwgcGNpZS0+bG5rY2FwKTsKCmxua2NhcCBpcyBhIDMyLWJp dCB2YXJpYWJsZSwgc28geW91IHNob3VsZCB1c2UgZHdfcGNpZV93cml0ZWxfZGJpKCkuCgotIE1h bmkKCj4gKwkJZHdfcGNpZV9kYmlfcm9fd3JfZGlzKHBjaSk7Cj4gKwo+ICAJCWNmZyA9IGxzX2x1 dF9yZWFkbChwY2llLCBQRVhfUEYwX0NPTkZJRyk7Cj4gIAkJY2ZnIHw9IFBFWF9QRjBfQ0ZHX1JF QURZOwo+ICAJCWxzX2x1dF93cml0ZWwocGNpZSwgUEVYX1BGMF9DT05GSUcsIGNmZyk7Cj4gQEAg LTIxNiw2ICsyMjUsNyBAQCBzdGF0aWMgaW50IF9faW5pdCBsc19wY2llX2VwX3Byb2JlKHN0cnVj dCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gIAlzdHJ1Y3QgbHNfcGNpZV9lcCAqcGNpZTsKPiAg CXN0cnVjdCBwY2lfZXBjX2ZlYXR1cmVzICpsc19lcGM7Cj4gIAlzdHJ1Y3QgcmVzb3VyY2UgKmRi aV9iYXNlOwo+ICsJdTggb2Zmc2V0Owo+ICAJaW50IHJldDsKPiAgCj4gIAlwY2llID0gZGV2bV9r emFsbG9jKGRldiwgc2l6ZW9mKCpwY2llKSwgR0ZQX0tFUk5FTCk7Cj4gQEAgLTI1Miw2ICsyNjIs OSBAQCBzdGF0aWMgaW50IF9faW5pdCBsc19wY2llX2VwX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9k ZXZpY2UgKnBkZXYpCj4gIAo+ICAJcGxhdGZvcm1fc2V0X2RydmRhdGEocGRldiwgcGNpZSk7Cj4g IAo+ICsJb2Zmc2V0ID0gZHdfcGNpZV9maW5kX2NhcGFiaWxpdHkocGNpLCBQQ0lfQ0FQX0lEX0VY UCk7Cj4gKwlwY2llLT5sbmtjYXAgPSBkd19wY2llX3JlYWRsX2RiaShwY2ksIG9mZnNldCArIFBD SV9FWFBfTE5LQ0FQKTsKPiArCj4gIAlyZXQgPSBkd19wY2llX2VwX2luaXQoJnBjaS0+ZXApOwo+ ICAJaWYgKHJldCkKPiAgCQlyZXR1cm4gcmV0Owo+IC0tIAo+IDIuMzQuMQo+IAoKLS0gCuCuruCu o+Cuv+CuteCuo+CvjeCuo+CuqeCvjSDgrprgrqTgrr7grprgrr/grrXgrq7gr40KCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwg bWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8v bGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK