From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C84610E7 for ; Mon, 17 Jul 2023 16:45:37 +0000 (UTC) Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1b89d47ffb6so25968995ad.2 for ; Mon, 17 Jul 2023 09:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689612337; x=1692204337; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=5QsGRkh6jSTBK3lt0PkwQlq6Yn1SGLWvs1rGiyZyQiw=; b=ALTAoztWCBNmZ6fN1PurRBYRXLjiLIVJL2YyQWp0DropkX4+GSNg/7RReJVbxxxF9m m9iUwe619PtnfAy1yGg/Wzzs9YrH5e6Tf35zL5cLQZBpjoO7s8Ep4nmYmLeat6XmXX2o k+eZZ9bOfQQVkdLCHxicc84NH3y+Zq7j4h7cYrUdVezTMjpMMEPjYmnOGVD1Z74VtTPb hJqaFdbtxj0QzTnBys8nJQt+pmyZU1zrrOxWIA+tfXJxv0af33yfObybt9U8TFZ4doKJ DspHzf6dxQRqShdYk2tzzHBmGYqRdkpR1l75fxgT2DdTFXYQzakefdEcI07CdpDwFUKN kaNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689612337; x=1692204337; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5QsGRkh6jSTBK3lt0PkwQlq6Yn1SGLWvs1rGiyZyQiw=; b=kuxdoQYU5IOyCimfabB37F6InGZOuLYYW/QLpMBVraTGFaxfRD6RmaojSktg09TNB9 CZvFfMNEF5ejJk3FR3BWxHhBNWnyYp81vsCCt/sLjj99Ci0/jE7VzTHbOW9lud/xcwLE y6k8FM1pVawi1dzzeb+7Vmy1YfFf3Amif2Q6ip9SX6JsjWDt3zd05gZnJIYLH6R5MQgU sTPAjCTyubK7hOjw2LuWV55T5CoD/4vU6k4XBV21qJUVDWFb/DimXOfU9XhMke+P5fVu 1JmE83muqy4z7CPgqcMyNGcdCaxbwB8k4ckHFdseG/jI+FpPMD+KVDj3g8t7oU6XVB3D w5Cw== X-Gm-Message-State: ABy/qLYFMCtEi1lmSbLM4hGEXKRq2GN6Wtct+A9b+xuYKl5Qx1YgU7Ic W2NAHeKFaPpIfgVkSENjXkO/ X-Google-Smtp-Source: APBJJlEvYNyyUncRVmtB1UAc/qY5Euc5LgKlWHfDLBAhOQZWIBavmpXuRWPiQTEGvgXYWRU23MXhQA== X-Received: by 2002:a17:902:7c14:b0:1b8:3786:334d with SMTP id x20-20020a1709027c1400b001b83786334dmr2208512pll.18.1689612337328; Mon, 17 Jul 2023 09:45:37 -0700 (PDT) Received: from thinkpad ([117.217.190.73]) by smtp.gmail.com with ESMTPSA id 21-20020a170902c21500b001b7feed285csm133265pll.36.2023.07.17.09.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jul 2023 09:45:36 -0700 (PDT) Date: Mon, 17 Jul 2023 22:15:26 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: helgaas@kernel.org, imx@lists.linux.dev, bhelgaas@google.com, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com, kw@linux.com, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, minghuan.lian@nxp.com, mingkai.hu@nxp.com, robh+dt@kernel.org, roy.zang@nxp.com, shawnguo@kernel.org, zhiqiang.hou@nxp.com Subject: Re: [PATCH v3 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions Message-ID: <20230717164526.GC35455@thinkpad> References: <20230419164118.596300-1-Frank.Li@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230419164118.596300-1-Frank.Li@nxp.com> On Wed, Apr 19, 2023 at 12:41:17PM -0400, Frank Li wrote: > Introduced helper function dw_pcie_get_ltssm to retrieve SMLH_LTSS_STATE. > Added API pme_turn_off and exit_from_l2 for managing L2/L3 state transitions. > > Typical L2 entry workflow: > > 1. Transmit PME turn off signal to PCI devices. > 2. Await link entering L2_IDLE state. AFAIK, typical workflow is to wait for PME_To_Ack. > 3. Transition Root complex to D3 state. > > Typical L2 exit workflow: > > 1. Transition Root complex to D0 state. > 2. Issue exit from L2 command. > 3. Reinitialize PCI host. > 4. Wait for link to become active. > > Signed-off-by: Frank Li > --- > Change from v2 to v3: > - Basic rewrite whole patch according rob herry suggestion. > put common function into dwc, so more soc can share the same logic. > > .../pci/controller/dwc/pcie-designware-host.c | 80 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 28 +++++++ > 2 files changed, 108 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 9952057c8819..ef6869488bde 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -8,6 +8,7 @@ > * Author: Jingoo Han > */ > > +#include > #include > #include > #include > @@ -807,3 +808,82 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > return 0; > } > EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); > + > +/* > + * There are for configuring host controllers, which are bridges *to* PCI devices > + * but are not PCI devices themselves. None of the functions applicable to the devices. So there is no need for this comment. > + */ > +static void dw_pcie_set_dstate(struct dw_pcie *pci, u32 dstate) Please use pci_power_t defines for dstates. > +{ > + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM); > + u32 val; > + > + val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL); Please use PCI accessors for accessing spec compliant registers. > + val &= ~PCI_PM_CTRL_STATE_MASK; > + val |= dstate; > + dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val); > +} > + > +int dw_pcie_suspend_noirq(struct dw_pcie *pci) > +{ > + u32 val; > + int ret; > + > + if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) > + return 0; > + > + pci->pp.ops->pme_turn_off(&pci->pp); You should first check for the existence of the callback before invoking. This applies to all callbacks in this patch. > + > + /* > + * PCI Express Base Specification Rev 4.0 > + * 5.3.3.2.1 PME Synchronization > + * Recommand 1ms to 10ms timeout to check L2 ready > + */ > + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, > + 100, 10000, false, pci); Is there no way to wait for PME_To_Ack TLP? > + if (ret) { > + dev_err(pci->dev, "PCIe link enter L2 timeout! ltssm = 0x%x\n", val); > + return ret; > + } > + > + dw_pcie_set_dstate(pci, 0x3); > + > + pci->suspended = true; > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); > + > +int dw_pcie_resume_noirq(struct dw_pcie *pci) > +{ > + int ret; > + > + if (!pci->suspended) > + return 0; > + > + pci->suspended = false; > + > + dw_pcie_set_dstate(pci, 0x0); > + > + pci->pp.ops->exit_from_l2(&pci->pp); > + > + /* delay 10 ms to access EP */ Is this delay as part of the DWC spec? If so, please quote the section. > + mdelay(10); > + > + ret = pci->pp.ops->host_init(&pci->pp); > + if (ret) { > + dev_err(pci->dev, "ls_pcie_host_init failed! ret = 0x%x\n", ret); s/ls_pcie_host_init/Host init > + return ret; > + } > + > + dw_pcie_setup_rc(&pci->pp); > + Don't you need to configure iATU? > + ret = dw_pcie_wait_for_link(pci); Don't you need to start the link beforehand? > + if (ret) { > + dev_err(pci->dev, "wait link up timeout! ret = 0x%x\n", ret); dw_pcie_wait_for_link() itself prints error message on failure. So no need to do the same here. - Mani > + return ret; > + } > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 79713ce075cc..effb07a506e4 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -288,10 +288,21 @@ enum dw_pcie_core_rst { > DW_PCIE_NUM_CORE_RSTS > }; > > +enum dw_pcie_ltssm { > + DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, > + /* Need align PCIE_PORT_DEBUG0 bit0:5 */ > + DW_PCIE_LTSSM_DETECT_QUIET = 0x0, > + DW_PCIE_LTSSM_DETECT_ACT = 0x1, > + DW_PCIE_LTSSM_L0 = 0x11, > + DW_PCIE_LTSSM_L2_IDLE = 0x15, > +}; > + > struct dw_pcie_host_ops { > int (*host_init)(struct dw_pcie_rp *pp); > void (*host_deinit)(struct dw_pcie_rp *pp); > int (*msi_host_init)(struct dw_pcie_rp *pp); > + void (*pme_turn_off)(struct dw_pcie_rp *pp); > + void (*exit_from_l2)(struct dw_pcie_rp *pp); > }; > > struct dw_pcie_rp { > @@ -364,6 +375,7 @@ struct dw_pcie_ops { > void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, > size_t size, u32 val); > int (*link_up)(struct dw_pcie *pcie); > + enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); > int (*start_link)(struct dw_pcie *pcie); > void (*stop_link)(struct dw_pcie *pcie); > }; > @@ -393,6 +405,7 @@ struct dw_pcie { > struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; > struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; > struct gpio_desc *pe_rst; > + bool suspended; > }; > > #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) > @@ -430,6 +443,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci); > int dw_pcie_edma_detect(struct dw_pcie *pci); > void dw_pcie_edma_remove(struct dw_pcie *pci); > > +int dw_pcie_suspend_noirq(struct dw_pcie *pci); > +int dw_pcie_resume_noirq(struct dw_pcie *pci); > + > static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) > { > dw_pcie_write_dbi(pci, reg, 0x4, val); > @@ -501,6 +517,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) > pci->ops->stop_link(pci); > } > > +static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) > +{ > + u32 val; > + > + if (pci->ops && pci->ops->get_ltssm) > + return pci->ops->get_ltssm(pci); > + > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); > + > + return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val); > +} > + > #ifdef CONFIG_PCIE_DW_HOST > irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); > int dw_pcie_setup_rc(struct dw_pcie_rp *pp); > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம் From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qLRLw-004a3b-0T for linux-arm-kernel@lists.infradead.org; Mon, 17 Jul 2023 16:45:42 +0000 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1b8bbcfd89aso26121175ad.1 for ; Mon, 17 Jul 2023 09:45:37 -0700 (PDT) Date: Mon, 17 Jul 2023 22:15:26 +0530 From: Manivannan Sadhasivam Subject: Re: [PATCH v3 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions Message-ID: <20230717164526.GC35455@thinkpad> References: <20230419164118.596300-1-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230419164118.596300-1-Frank.Li@nxp.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+lwn-linux-arm-kernel=archive.lwn.net@lists.infradead.org List-Archive: To: Frank Li Cc: helgaas@kernel.org, imx@lists.linux.dev, bhelgaas@google.com, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com, kw@linux.com, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, minghuan.lian@nxp.com, mingkai.hu@nxp.com, robh+dt@kernel.org, roy.zang@nxp.com, shawnguo@kernel.org, zhiqiang.hou@nxp.com T24gV2VkLCBBcHIgMTksIDIwMjMgYXQgMTI6NDE6MTdQTSAtMDQwMCwgRnJhbmsgTGkgd3JvdGU6 Cj4gSW50cm9kdWNlZCBoZWxwZXIgZnVuY3Rpb24gZHdfcGNpZV9nZXRfbHRzc20gdG8gcmV0cmll dmUgU01MSF9MVFNTX1NUQVRFLgo+IEFkZGVkIEFQSSBwbWVfdHVybl9vZmYgYW5kIGV4aXRfZnJv bV9sMiBmb3IgbWFuYWdpbmcgTDIvTDMgc3RhdGUgdHJhbnNpdGlvbnMuCj4gCj4gVHlwaWNhbCBM MiBlbnRyeSB3b3JrZmxvdzoKPiAKPiAxLiBUcmFuc21pdCBQTUUgdHVybiBvZmYgc2lnbmFsIHRv IFBDSSBkZXZpY2VzLgo+IDIuIEF3YWl0IGxpbmsgZW50ZXJpbmcgTDJfSURMRSBzdGF0ZS4KCkFG QUlLLCB0eXBpY2FsIHdvcmtmbG93IGlzIHRvIHdhaXQgZm9yIFBNRV9Ub19BY2suCgo+IDMuIFRy YW5zaXRpb24gUm9vdCBjb21wbGV4IHRvIEQzIHN0YXRlLgo+IAo+IFR5cGljYWwgTDIgZXhpdCB3 b3JrZmxvdzoKPiAKPiAxLiBUcmFuc2l0aW9uIFJvb3QgY29tcGxleCB0byBEMCBzdGF0ZS4KPiAy LiBJc3N1ZSBleGl0IGZyb20gTDIgY29tbWFuZC4KPiAzLiBSZWluaXRpYWxpemUgUENJIGhvc3Qu Cj4gNC4gV2FpdCBmb3IgbGluayB0byBiZWNvbWUgYWN0aXZlLgo+IAo+IFNpZ25lZC1vZmYtYnk6 IEZyYW5rIExpIDxGcmFuay5MaUBueHAuY29tPgo+IC0tLQo+IENoYW5nZSBmcm9tIHYyIHRvIHYz OiAKPiAtIEJhc2ljIHJld3JpdGUgd2hvbGUgcGF0Y2ggYWNjb3JkaW5nIHJvYiBoZXJyeSBzdWdn ZXN0aW9uLiAKPiAgIHB1dCBjb21tb24gZnVuY3Rpb24gaW50byBkd2MsIHNvIG1vcmUgc29jIGNh biBzaGFyZSB0aGUgc2FtZSBsb2dpYy4KPiAgIAo+ICAuLi4vcGNpL2NvbnRyb2xsZXIvZHdjL3Bj aWUtZGVzaWdud2FyZS1ob3N0LmMgfCA4MCArKysrKysrKysrKysrKysrKysrCj4gIGRyaXZlcnMv cGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZGVzaWdud2FyZS5oICB8IDI4ICsrKysrKysKPiAgMiBm aWxlcyBjaGFuZ2VkLCAxMDggaW5zZXJ0aW9ucygrKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJz L3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWRlc2lnbndhcmUtaG9zdC5jIGIvZHJpdmVycy9wY2kv Y29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLWhvc3QuYwo+IGluZGV4IDk5NTIwNTdjODgx OS4uZWY2ODY5NDg4YmRlIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdj L3BjaWUtZGVzaWdud2FyZS1ob3N0LmMKPiArKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3 Yy9wY2llLWRlc2lnbndhcmUtaG9zdC5jCj4gQEAgLTgsNiArOCw3IEBACj4gICAqIEF1dGhvcjog SmluZ29vIEhhbiA8amcxLmhhbkBzYW1zdW5nLmNvbT4KPiAgICovCj4gIAo+ICsjaW5jbHVkZSA8 bGludXgvaW9wb2xsLmg+Cj4gICNpbmNsdWRlIDxsaW51eC9pcnFjaGlwL2NoYWluZWRfaXJxLmg+ Cj4gICNpbmNsdWRlIDxsaW51eC9pcnFkb21haW4uaD4KPiAgI2luY2x1ZGUgPGxpbnV4L21zaS5o Pgo+IEBAIC04MDcsMyArODA4LDgyIEBAIGludCBkd19wY2llX3NldHVwX3JjKHN0cnVjdCBkd19w Y2llX3JwICpwcCkKPiAgCXJldHVybiAwOwo+ICB9Cj4gIEVYUE9SVF9TWU1CT0xfR1BMKGR3X3Bj aWVfc2V0dXBfcmMpOwo+ICsKPiArLyoKPiArICogVGhlcmUgYXJlIGZvciBjb25maWd1cmluZyBo b3N0IGNvbnRyb2xsZXJzLCB3aGljaCBhcmUgYnJpZGdlcyAqdG8qIFBDSSBkZXZpY2VzCj4gKyAq IGJ1dCBhcmUgbm90IFBDSSBkZXZpY2VzIHRoZW1zZWx2ZXMuCgpOb25lIG9mIHRoZSBmdW5jdGlv bnMgYXBwbGljYWJsZSB0byB0aGUgZGV2aWNlcy4gU28gdGhlcmUgaXMgbm8gbmVlZCBmb3IgdGhp cwpjb21tZW50LgoKPiArICovCj4gK3N0YXRpYyB2b2lkIGR3X3BjaWVfc2V0X2RzdGF0ZShzdHJ1 Y3QgZHdfcGNpZSAqcGNpLCB1MzIgZHN0YXRlKQoKUGxlYXNlIHVzZSBwY2lfcG93ZXJfdCBkZWZp bmVzIGZvciBkc3RhdGVzLgoKPiArewo+ICsJdTggb2Zmc2V0ID0gZHdfcGNpZV9maW5kX2NhcGFi aWxpdHkocGNpLCBQQ0lfQ0FQX0lEX1BNKTsKPiArCXUzMiB2YWw7Cj4gKwo+ICsJdmFsID0gZHdf cGNpZV9yZWFkd19kYmkocGNpLCBvZmZzZXQgKyBQQ0lfUE1fQ1RSTCk7CgpQbGVhc2UgdXNlIFBD SSBhY2Nlc3NvcnMgZm9yIGFjY2Vzc2luZyBzcGVjIGNvbXBsaWFudCByZWdpc3RlcnMuCgo+ICsJ dmFsICY9IH5QQ0lfUE1fQ1RSTF9TVEFURV9NQVNLOwo+ICsJdmFsIHw9IGRzdGF0ZTsKPiArCWR3 X3BjaWVfd3JpdGV3X2RiaShwY2ksIG9mZnNldCArIFBDSV9QTV9DVFJMLCB2YWwpOwo+ICt9Cj4g Kwo+ICtpbnQgZHdfcGNpZV9zdXNwZW5kX25vaXJxKHN0cnVjdCBkd19wY2llICpwY2kpCj4gK3sK PiArCXUzMiB2YWw7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCWlmIChkd19wY2llX2dldF9sdHNzbShw Y2kpIDw9IERXX1BDSUVfTFRTU01fREVURUNUX0FDVCkKPiArCQlyZXR1cm4gMDsKPiArCj4gKwlw Y2ktPnBwLm9wcy0+cG1lX3R1cm5fb2ZmKCZwY2ktPnBwKTsKCllvdSBzaG91bGQgZmlyc3QgY2hl Y2sgZm9yIHRoZSBleGlzdGVuY2Ugb2YgdGhlIGNhbGxiYWNrIGJlZm9yZSBpbnZva2luZy4gVGhp cwphcHBsaWVzIHRvIGFsbCBjYWxsYmFja3MgaW4gdGhpcyBwYXRjaC4KCj4gKwo+ICsJLyoKPiAr CSAqIFBDSSBFeHByZXNzIEJhc2UgU3BlY2lmaWNhdGlvbiBSZXYgNC4wCj4gKwkgKiA1LjMuMy4y LjEgUE1FIFN5bmNocm9uaXphdGlvbgo+ICsJICogUmVjb21tYW5kIDFtcyB0byAxMG1zIHRpbWVv dXQgdG8gY2hlY2sgTDIgcmVhZHkKPiArCSAqLwo+ICsJcmV0ID0gcmVhZF9wb2xsX3RpbWVvdXQo ZHdfcGNpZV9nZXRfbHRzc20sIHZhbCwgdmFsID09IERXX1BDSUVfTFRTU01fTDJfSURMRSwKPiAr CQkJCTEwMCwgMTAwMDAsIGZhbHNlLCBwY2kpOwoKSXMgdGhlcmUgbm8gd2F5IHRvIHdhaXQgZm9y IFBNRV9Ub19BY2sgVExQPwoKPiArCWlmIChyZXQpIHsKPiArCQlkZXZfZXJyKHBjaS0+ZGV2LCAi UENJZSBsaW5rIGVudGVyIEwyIHRpbWVvdXQhIGx0c3NtID0gMHgleFxuIiwgdmFsKTsKPiArCQly ZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCWR3X3BjaWVfc2V0X2RzdGF0ZShwY2ksIDB4Myk7Cj4g Kwo+ICsJcGNpLT5zdXNwZW5kZWQgPSB0cnVlOwo+ICsKPiArCXJldHVybiByZXQ7Cj4gK30KPiAr RVhQT1JUX1NZTUJPTF9HUEwoZHdfcGNpZV9zdXNwZW5kX25vaXJxKTsKPiArCj4gK2ludCBkd19w Y2llX3Jlc3VtZV9ub2lycShzdHJ1Y3QgZHdfcGNpZSAqcGNpKQo+ICt7Cj4gKwlpbnQgcmV0Owo+ ICsKPiArCWlmICghcGNpLT5zdXNwZW5kZWQpCj4gKwkJcmV0dXJuIDA7Cj4gKwo+ICsJcGNpLT5z dXNwZW5kZWQgPSBmYWxzZTsKPiArCj4gKwlkd19wY2llX3NldF9kc3RhdGUocGNpLCAweDApOwo+ ICsKPiArCXBjaS0+cHAub3BzLT5leGl0X2Zyb21fbDIoJnBjaS0+cHApOwo+ICsKPiArCS8qIGRl bGF5IDEwIG1zIHRvIGFjY2VzcyBFUCAqLwoKSXMgdGhpcyBkZWxheSBhcyBwYXJ0IG9mIHRoZSBE V0Mgc3BlYz8gSWYgc28sIHBsZWFzZSBxdW90ZSB0aGUgc2VjdGlvbi4KCj4gKwltZGVsYXkoMTAp Owo+ICsKPiArCXJldCA9IHBjaS0+cHAub3BzLT5ob3N0X2luaXQoJnBjaS0+cHApOwo+ICsJaWYg KHJldCkgewo+ICsJCWRldl9lcnIocGNpLT5kZXYsICJsc19wY2llX2hvc3RfaW5pdCBmYWlsZWQh IHJldCA9IDB4JXhcbiIsIHJldCk7CgpzL2xzX3BjaWVfaG9zdF9pbml0L0hvc3QgaW5pdAoKPiAr CQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiArCWR3X3BjaWVfc2V0dXBfcmMoJnBjaS0+cHApOwo+ ICsKCkRvbid0IHlvdSBuZWVkIHRvIGNvbmZpZ3VyZSBpQVRVPwoKPiArCXJldCA9IGR3X3BjaWVf d2FpdF9mb3JfbGluayhwY2kpOwoKRG9uJ3QgeW91IG5lZWQgdG8gc3RhcnQgdGhlIGxpbmsgYmVm b3JlaGFuZD8KCj4gKwlpZiAocmV0KSB7Cj4gKwkJZGV2X2VycihwY2ktPmRldiwgIndhaXQgbGlu ayB1cCB0aW1lb3V0ISByZXQgPSAweCV4XG4iLCByZXQpOwoKZHdfcGNpZV93YWl0X2Zvcl9saW5r KCkgaXRzZWxmIHByaW50cyBlcnJvciBtZXNzYWdlIG9uIGZhaWx1cmUuIFNvIG5vIG5lZWQgdG8g ZG8KdGhlIHNhbWUgaGVyZS4KCi0gTWFuaQoKPiArCQlyZXR1cm4gcmV0Owo+ICsJfQo+ICsKPiAr CXJldHVybiByZXQ7Cj4gK30KPiArRVhQT1JUX1NZTUJPTF9HUEwoZHdfcGNpZV9yZXN1bWVfbm9p cnEpOwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWRlc2ln bndhcmUuaCBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZGVzaWdud2FyZS5oCj4g aW5kZXggNzk3MTNjZTA3NWNjLi5lZmZiMDdhNTA2ZTQgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9w Y2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmgKPiArKysgYi9kcml2ZXJzL3BjaS9j b250cm9sbGVyL2R3Yy9wY2llLWRlc2lnbndhcmUuaAo+IEBAIC0yODgsMTAgKzI4OCwyMSBAQCBl bnVtIGR3X3BjaWVfY29yZV9yc3Qgewo+ICAJRFdfUENJRV9OVU1fQ09SRV9SU1RTCj4gIH07Cj4g IAo+ICtlbnVtIGR3X3BjaWVfbHRzc20gewo+ICsJRFdfUENJRV9MVFNTTV9VTktOT1dOID0gMHhG RkZGRkZGRiwKPiArCS8qIE5lZWQgYWxpZ24gUENJRV9QT1JUX0RFQlVHMCBiaXQwOjUgKi8KPiAr CURXX1BDSUVfTFRTU01fREVURUNUX1FVSUVUID0gMHgwLAo+ICsJRFdfUENJRV9MVFNTTV9ERVRF Q1RfQUNUID0gMHgxLAo+ICsJRFdfUENJRV9MVFNTTV9MMCA9IDB4MTEsCj4gKwlEV19QQ0lFX0xU U1NNX0wyX0lETEUgPSAweDE1LAo+ICt9Owo+ICsKPiAgc3RydWN0IGR3X3BjaWVfaG9zdF9vcHMg ewo+ICAJaW50ICgqaG9zdF9pbml0KShzdHJ1Y3QgZHdfcGNpZV9ycCAqcHApOwo+ICAJdm9pZCAo Kmhvc3RfZGVpbml0KShzdHJ1Y3QgZHdfcGNpZV9ycCAqcHApOwo+ICAJaW50ICgqbXNpX2hvc3Rf aW5pdCkoc3RydWN0IGR3X3BjaWVfcnAgKnBwKTsKPiArCXZvaWQgKCpwbWVfdHVybl9vZmYpKHN0 cnVjdCBkd19wY2llX3JwICpwcCk7Cj4gKwl2b2lkICgqZXhpdF9mcm9tX2wyKShzdHJ1Y3QgZHdf cGNpZV9ycCAqcHApOwo+ICB9Owo+ICAKPiAgc3RydWN0IGR3X3BjaWVfcnAgewo+IEBAIC0zNjQs NiArMzc1LDcgQEAgc3RydWN0IGR3X3BjaWVfb3BzIHsKPiAgCXZvaWQgICAgKCp3cml0ZV9kYmky KShzdHJ1Y3QgZHdfcGNpZSAqcGNpZSwgdm9pZCBfX2lvbWVtICpiYXNlLCB1MzIgcmVnLAo+ICAJ CQkgICAgICBzaXplX3Qgc2l6ZSwgdTMyIHZhbCk7Cj4gIAlpbnQJKCpsaW5rX3VwKShzdHJ1Y3Qg ZHdfcGNpZSAqcGNpZSk7Cj4gKwllbnVtIGR3X3BjaWVfbHRzc20gKCpnZXRfbHRzc20pKHN0cnVj dCBkd19wY2llICpwY2llKTsKPiAgCWludAkoKnN0YXJ0X2xpbmspKHN0cnVjdCBkd19wY2llICpw Y2llKTsKPiAgCXZvaWQJKCpzdG9wX2xpbmspKHN0cnVjdCBkd19wY2llICpwY2llKTsKPiAgfTsK PiBAQCAtMzkzLDYgKzQwNSw3IEBAIHN0cnVjdCBkd19wY2llIHsKPiAgCXN0cnVjdCByZXNldF9j b250cm9sX2J1bGtfZGF0YQlhcHBfcnN0c1tEV19QQ0lFX05VTV9BUFBfUlNUU107Cj4gIAlzdHJ1 Y3QgcmVzZXRfY29udHJvbF9idWxrX2RhdGEJY29yZV9yc3RzW0RXX1BDSUVfTlVNX0NPUkVfUlNU U107Cj4gIAlzdHJ1Y3QgZ3Bpb19kZXNjCQkqcGVfcnN0Owo+ICsJYm9vbAkJCXN1c3BlbmRlZDsK PiAgfTsKPiAgCj4gICNkZWZpbmUgdG9fZHdfcGNpZV9mcm9tX3BwKHBvcnQpIGNvbnRhaW5lcl9v ZigocG9ydCksIHN0cnVjdCBkd19wY2llLCBwcCkKPiBAQCAtNDMwLDYgKzQ0Myw5IEBAIHZvaWQg ZHdfcGNpZV9pYXR1X2RldGVjdChzdHJ1Y3QgZHdfcGNpZSAqcGNpKTsKPiAgaW50IGR3X3BjaWVf ZWRtYV9kZXRlY3Qoc3RydWN0IGR3X3BjaWUgKnBjaSk7Cj4gIHZvaWQgZHdfcGNpZV9lZG1hX3Jl bW92ZShzdHJ1Y3QgZHdfcGNpZSAqcGNpKTsKPiAgCj4gK2ludCBkd19wY2llX3N1c3BlbmRfbm9p cnEoc3RydWN0IGR3X3BjaWUgKnBjaSk7Cj4gK2ludCBkd19wY2llX3Jlc3VtZV9ub2lycShzdHJ1 Y3QgZHdfcGNpZSAqcGNpKTsKPiArCj4gIHN0YXRpYyBpbmxpbmUgdm9pZCBkd19wY2llX3dyaXRl bF9kYmkoc3RydWN0IGR3X3BjaWUgKnBjaSwgdTMyIHJlZywgdTMyIHZhbCkKPiAgewo+ICAJZHdf cGNpZV93cml0ZV9kYmkocGNpLCByZWcsIDB4NCwgdmFsKTsKPiBAQCAtNTAxLDYgKzUxNywxOCBA QCBzdGF0aWMgaW5saW5lIHZvaWQgZHdfcGNpZV9zdG9wX2xpbmsoc3RydWN0IGR3X3BjaWUgKnBj aSkKPiAgCQlwY2ktPm9wcy0+c3RvcF9saW5rKHBjaSk7Cj4gIH0KPiAgCj4gK3N0YXRpYyBpbmxp bmUgZW51bSBkd19wY2llX2x0c3NtIGR3X3BjaWVfZ2V0X2x0c3NtKHN0cnVjdCBkd19wY2llICpw Y2kpCj4gK3sKPiArCXUzMiB2YWw7Cj4gKwo+ICsJaWYgKHBjaS0+b3BzICYmIHBjaS0+b3BzLT5n ZXRfbHRzc20pCj4gKwkJcmV0dXJuIHBjaS0+b3BzLT5nZXRfbHRzc20ocGNpKTsKPiArCj4gKwl2 YWwgPSBkd19wY2llX3JlYWRsX2RiaShwY2ksIFBDSUVfUE9SVF9ERUJVRzApOwo+ICsKPiArCXJl dHVybiAoZW51bSBkd19wY2llX2x0c3NtKUZJRUxEX0dFVChQT1JUX0xPR0lDX0xUU1NNX1NUQVRF X01BU0ssIHZhbCk7Cj4gK30KPiArCj4gICNpZmRlZiBDT05GSUdfUENJRV9EV19IT1NUCj4gIGly cXJldHVybl90IGR3X2hhbmRsZV9tc2lfaXJxKHN0cnVjdCBkd19wY2llX3JwICpwcCk7Cj4gIGlu dCBkd19wY2llX3NldHVwX3JjKHN0cnVjdCBkd19wY2llX3JwICpwcCk7Cj4gLS0gCj4gMi4zNC4x Cj4gCgotLSAK4K6u4K6j4K6/4K614K6j4K+N4K6j4K6p4K+NIOCumuCupOCuvuCumuCuv+CuteCu ruCvjQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlu dXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRl YWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgt YXJtLWtlcm5lbAo=