Re: [PATCH v3 3/3] iio: Add driver for Murata IRS-D200

[kernel test robot <lkp@intel.com>]

Hi Waqar,

kernel test robot noticed the following build errors:

[auto build test ERROR on 3f01e9fed8454dcd89727016c3e5b2fbb8f8e50c]

url:    https://github.com/intel-lab-lkp/linux/commits/Waqar-Hameed/dt-bindings-iio-proximity-Add-Murata-IRS-D200/20230718-203520
base:   3f01e9fed8454dcd89727016c3e5b2fbb8f8e50c
patch link:    https://lore.kernel.org/r/39cfb5b9f58e26a9b348a03743d250249983ed35.1689683411.git.waqar.hameed%40axis.com
patch subject: [PATCH v3 3/3] iio: Add driver for Murata IRS-D200
config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20230719/202307190824.LNgDNyW1-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230719/202307190824.LNgDNyW1-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307190824.LNgDNyW1-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/iio/proximity/irsd200.c: In function 'irsd200_irq_thread':
>> drivers/iio/proximity/irsd200.c:705:17: error: implicit declaration of function 'iio_trigger_poll_chained'; did you mean 'iio_trigger_poll_nested'? [-Werror=implicit-function-declaration]
     705 |                 iio_trigger_poll_chained(indio_dev->trig);
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~
         |                 iio_trigger_poll_nested
   cc1: some warnings being treated as errors


vim +705 drivers/iio/proximity/irsd200.c

   676	
   677	static irqreturn_t irsd200_irq_thread(int irq, void *dev_id)
   678	{
   679		struct iio_dev *indio_dev = dev_id;
   680		struct irsd200_data *data = iio_priv(indio_dev);
   681		enum iio_event_direction dir;
   682		unsigned int lower_count;
   683		unsigned int upper_count;
   684		unsigned int status = 0;
   685		unsigned int source = 0;
   686		unsigned int clear = 0;
   687		unsigned int count = 0;
   688		int ret;
   689	
   690		ret = regmap_read(data->regmap, IRS_REG_INTR, &source);
   691		if (ret) {
   692			dev_err(data->dev, "Could not read interrupt source (%d)\n",
   693				ret);
   694			return IRQ_HANDLED;
   695		}
   696	
   697		ret = regmap_read(data->regmap, IRS_REG_STATUS, &status);
   698		if (ret) {
   699			dev_err(data->dev, "Could not acknowledge interrupt (%d)\n",
   700				ret);
   701			return IRQ_HANDLED;
   702		}
   703	
   704		if (status & BIT(IRS_INTR_DATA) && iio_buffer_enabled(indio_dev)) {
 > 705			iio_trigger_poll_chained(indio_dev->trig);
   706			clear |= BIT(IRS_INTR_DATA);
   707		}
   708	
   709		if (status & BIT(IRS_INTR_COUNT_THR_OR) &&
   710		    source & BIT(IRS_INTR_COUNT_THR_OR)) {
   711			/*
   712			 * The register value resets to zero after reading. We therefore
   713			 * need to read once and manually extract the lower and upper
   714			 * count register fields.
   715			 */
   716			ret = regmap_read(data->regmap, IRS_REG_COUNT, &count);
   717			if (ret)
   718				dev_err(data->dev, "Could not read count (%d)\n", ret);
   719	
   720			upper_count = IRS_UPPER_COUNT(count);
   721			lower_count = IRS_LOWER_COUNT(count);
   722	
   723			/*
   724			 * We only check the OR mode to be able to push events for
   725			 * rising and falling thresholds. AND mode is covered when both
   726			 * upper and lower count is non-zero, and is signaled with
   727			 * IIO_EV_DIR_EITHER.
   728			 */
   729			if (upper_count && !lower_count)
   730				dir = IIO_EV_DIR_RISING;
   731			else if (!upper_count && lower_count)
   732				dir = IIO_EV_DIR_FALLING;
   733			else
   734				dir = IIO_EV_DIR_EITHER;
   735	
   736			iio_push_event(indio_dev,
   737				       IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, 0,
   738							    IIO_EV_TYPE_THRESH, dir),
   739				       iio_get_time_ns(indio_dev));
   740	
   741			/*
   742			 * The OR mode will always trigger when the AND mode does, but
   743			 * not vice versa. However, it seems like the AND bit needs to
   744			 * be cleared if data capture _and_ threshold count interrupts
   745			 * are desirable, even though it hasn't explicitly been selected
   746			 * (with IRS_REG_INTR). Either way, it doesn't hurt...
   747			 */
   748			clear |= BIT(IRS_INTR_COUNT_THR_OR) |
   749				 BIT(IRS_INTR_COUNT_THR_AND);
   750		}
   751	
   752		if (clear) {
   753			ret = regmap_write(data->regmap, IRS_REG_STATUS, clear);
   754			if (ret)
   755				dev_err(data->dev,
   756					"Could not clear interrupt status (%d)\n", ret);
   757		}
   758	
   759		return clear ? IRQ_HANDLED : IRQ_NONE;
   760	}
   761	

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