From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96F7EC001E0 for ; Thu, 27 Jul 2023 08:04:44 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CAA4586846; Thu, 27 Jul 2023 10:04:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="gthqJSei"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 87DC48688F; Thu, 27 Jul 2023 10:01:57 +0200 (CEST) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 00FD986834 for ; Thu, 27 Jul 2023 10:00:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=nm@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 36R80TPI083674; Thu, 27 Jul 2023 03:00:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1690444829; bh=qW0Bv2jr3SY8W+FAafU7e0aqZFeaNUYf46Zn8vC0ZRU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gthqJSeiUnrFzOWa5bNoHlTYOpkUX+8sGVdlI6GtOg1BHAgJYAHALsHMQ9zM2kwGT IdtHS80Nil9qg9+q83jV8Q0b+JV/B6D2FuSqnKkgZhljAbL8ovnEDSnwv91JWGWsJs 42AMMU0QSNrnKP8Z+qF6Nha88xs0DxL/HbPtIfZ8= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 36R80TfS024074 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 27 Jul 2023 03:00:29 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 27 Jul 2023 03:00:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jul 2023 03:00:29 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36R80SGG011616; Thu, 27 Jul 2023 03:00:28 -0500 From: Nishanth Menon To: , Tom Rini CC: Wadim Egorov , Francesco Dolcini , Sjoerd Simons , Neha Malcom Francis , Bryan Brattlof , Vignesh Raghavendra , Marcel Ziswiler , Nikhil Jain , Nishanth Menon Subject: [PATCH 02/16] doc: board: ti: am62x/j7200: Update with common boot flow diagram Date: Thu, 27 Jul 2023 03:00:13 -0500 Message-ID: <20230727080027.2817701-3-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727080027.2817701-1-nm@ti.com> References: <20230727080027.2817701-1-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update the bootflow svg diagram and reuse across the platforms as they are common. Signed-off-by: Nishanth Menon --- doc/board/ti/am62x_sk.rst | 68 +- doc/board/ti/img/boot_diagram_k3_current.svg | 1987 ++++++++++++++++++ doc/board/ti/j7200_evm.rst | 85 +- 3 files changed, 1989 insertions(+), 151 deletions(-) create mode 100644 doc/board/ti/img/boot_diagram_k3_current.svg diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index ba017a2b489e..f511b5935c16 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -42,73 +42,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+ - | TIFS | Main R5 | A53 | - +------------------------------------------------------------------------+ - | +--------+ | | | - | | Reset | | | | - | +--------+ | | | - | : | | | - | +--------+ | +-----------+ | | - | | *ROM* |----------|-->| Reset rls | | | - | +--------+ | +-----------+ | | - | | | | : | | - | | ROM | | : | | - | |services| | : | | - | | | | +-------------+ | | - | | | | | *R5 ROM* | | | - | | | | +-------------+ | | - | | |<---------|---|Load and auth| | | - | | | | | tiboot3.bin | | | - | +--------+ | +-------------+ | | - | | |<---------|---| Load sysfw | | | - | | | | | part to TIFS| | | - | | | | | core | | | - | | | | +-------------+ | | - | | | | : | | - | | | | : | | - | | | | : | | - | | | | +-------------+ | | - | | | | | *R5 SPL* | | | - | | | | +-------------+ | | - | | | | | DDR | | | - | | | | | config | | | - | | | | +-------------+ | | - | | | | | Load | | | - | | | | | tispl.bin | | | - | | | | +-------------+ | | - | | | | | Load R5 | | | - | | | | | firmware | | | - | | | | +-------------+ | | - | | |<---------|---| Start A53 | | | - | | | | | and jump to | | | - | | | | | DM fw image | | | - | | | | +-------------+ | | - | | | | | +-----------+ | - | | |----------|-----------------------|---->| Reset rls | | - | | | | | +-----------+ | - | | TIFS | | | : | - | |Services| | | +-------------+ | - | | |<---------|-----------------------|---->|*TF-A/OP-TEE*| | - | | | | | +-------------+ | - | | | | | : | - | | | | | +-----------+ | - | | |<---------|-----------------------|---->| *A53 SPL* | | - | | | | | +-----------+ | - | | | | | | Load | | - | | | | | | u-boot.img| | - | | | | | +-----------+ | - | | | | | : | - | | | | | +-----------+ | - | | |<---------|-----------------------|---->| *U-Boot* | | - | | | | | +-----------+ | - | | | | | | prompt | | - | | |----------|-----------------------|-----+-----------+-----| - | +--------+ | | | - | | | | - +------------------------------------------------------------------------+ +.. image:: img/boot_diagram_k3_current.svg - Here TIFS acts as master and provides all the critical services. R5/A53 requests TIFS to get these services done as shown in the above diagram. diff --git a/doc/board/ti/img/boot_diagram_k3_current.svg b/doc/board/ti/img/boot_diagram_k3_current.svg new file mode 100644 index 000000000000..a3844242481a --- /dev/null +++ b/doc/board/ti/img/boot_diagram_k3_current.svg @@ -0,0 +1,1987 @@ + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load and auth tiboot3.bin + + + + Load and authtiboot3.bin + + + + + + + + + Load system +config data + + + + Load systemconfig data + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + Start DM + + + + Start DM + + + + + + + + + + Device Mgr + + + + Device Mgr + + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + + + + + + + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + + + + CortexR/M +C6x/C7x + + + + CortexR/MC7x/C6x. + + + + + + + + + + Aux F/w + + + + Aux F/w + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + + start TIFS + + + + start TIFS + + + + + + + + + TIFS + + + + TIFS + + + + + + + + + + Security enclave Boot Processor + + + + Security enclaveProcessor + + + + + + + + + + Boot Loader +Processor + + + + Boot LoaderProcessor + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary +Processor + + + + AuxiliaryProcessor + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboot3.bin + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + + Load system config data + + + + Load system config data + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + Load DM F/w + + + + Load DM F/w + + + + + + + + + + branch + + + + branch + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + TF-A  + + + + TF-A  + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex A SPL + + + + Cortex A SPL + + + + + + + + + + U-boot + + + + U-boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w + + + + Load Aux core f/w(optional) + + + + + + + + + Start Aux core + + + + Start Aux core(optional) + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst index f81e3f43b7d7..fea01b55e2a1 100644 --- a/doc/board/ti/j7200_evm.rst +++ b/doc/board/ti/j7200_evm.rst @@ -30,90 +30,7 @@ Boot Flow: ---------- Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+-----------------------+ - | DMSC | MCU R5 | A72 | MAIN R5/C7x | - +------------------------------------------------------------------------+-----------------------+ - | +--------+ | | | | - | | Reset | | | | | - | +--------+ | | | | - | : | | | | - | +--------+ | +-----------+ | | | - | | *ROM* |----------|-->| Reset rls | | | | - | +--------+ | +-----------+ | | | - | | | | : | | | - | | ROM | | : | | | - | |services| | : | | | - | | | | +-------------+ | | | - | | | | | *R5 ROM* | | | | - | | | | +-------------+ | | | - | | |<---------|---|Load and auth| | | | - | | | | | tiboot3.bin | | | | - | | Start | | +-------------+ | | | - | | TIFS |<---------|---| Start | | | | - | | | | | TIFS | | | | - | +--------+ | +-------------+ | | | - | : | | | | | | - | +---------+ | | Load | | | | - | | *TIFS* | | | system | | | | - | +---------+ | | Config data | | | | - | | |<--------|---| | | | | - | | | | +-------------+ | | | - | | | | : | | | - | | | | : | | | - | | | | : | | | - | | | | +-------------+ | | | - | | | | | *R5 SPL* | | | | - | | | | +-------------+ | | | - | | | | | DDR | | | | - | | | | | config | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | tispl.bin | | | | - | | | | +-------------+ | | | - | | | | | Load R5 | | | | - | | | | | firmware | | | | - | | | | +-------------+ | | | - | | |<--------|---| Start A72 | | | | - | | | | | and jump to | | | | - | | | | | DM fw image | | | | - | | | | +-------------+ | | | - | | | | | +-----------+ | | - | | |---------|-----------------------|---->| Reset rls | | | - | | | | | +-----------+ | | - | | TIFS | | | : | | - | |Services | | | +-------------+ | | - | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | - | | | | | +-------------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *A72 SPL* | | | - | | | | | +-----------+ | | - | | | | | | Load | | | - | | | | | | u-boot.img| | | - | | | | | +-----------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *U-Boot* | | | - | | | | | +-----------+ | | - | | | | | | prompt | | | - | | | | | +-----------+ | | - | | | | | | Load R5 | | | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | - | | | | | | Load C7 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | - | | | | | | +-----------+ | - | | | | | | | - | +---------+ | | | | - | | | | | - +------------------------------------------------------------------------+-----------------------+ +.. image:: img/boot_diagram_k3_current.svg - Here DMSC acts as master and provides all the critical services. R5/A72 requests DMSC to get these services done as shown in the above diagram. -- 2.40.0