From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 89848C001E0 for ; Thu, 27 Jul 2023 08:06:00 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 63ACC86784; Thu, 27 Jul 2023 10:05:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="vI5UKyNl"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id A7B5886895; Thu, 27 Jul 2023 10:02:19 +0200 (CEST) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 383D586828 for ; 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Thu, 27 Jul 2023 03:00:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 27 Jul 2023 03:00:29 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 36R80Tmq011655; Thu, 27 Jul 2023 03:00:29 -0500 From: Nishanth Menon To: , Tom Rini CC: Wadim Egorov , Francesco Dolcini , Sjoerd Simons , Neha Malcom Francis , Bryan Brattlof , Vignesh Raghavendra , Marcel Ziswiler , Nikhil Jain , Nishanth Menon Subject: [PATCH 04/16] doc: board: ti: j721e: Update with boot flow diagram Date: Thu, 27 Jul 2023 03:00:15 -0500 Message-ID: <20230727080027.2817701-5-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230727080027.2817701-1-nm@ti.com> References: <20230727080027.2817701-1-nm@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Update the bootflow svg diagram instead of the ascii version Signed-off-by: Nishanth Menon --- doc/board/ti/img/boot_diagram_j721e.svg | 2088 +++++++++++++++++++++++ doc/board/ti/j721e_evm.rst | 91 +- 2 files changed, 2089 insertions(+), 90 deletions(-) create mode 100644 doc/board/ti/img/boot_diagram_j721e.svg diff --git a/doc/board/ti/img/boot_diagram_j721e.svg b/doc/board/ti/img/boot_diagram_j721e.svg new file mode 100644 index 000000000000..e9a7fd304671 --- /dev/null +++ b/doc/board/ti/img/boot_diagram_j721e.svg @@ -0,0 +1,2088 @@ + + + + + + + + + + + + + Cortex-R + + + + Cortex-R + + + + + + + + + + ROM + + + + ROM + + + + + + + + + Load and auth tiboot3.bin + + + + Load and authtiboo3.bin + + + + + + + + + + Cortex-A + + + + Cortex-A + + + + + + + + + + Load system + + +config data + + + + Load systemconfig data + + + + + + + + + DDR Config + + + + DDR Config + + + + + + + + + Load tispl.bin + + + + Load tispl.bin + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + Start DM + + + + Start DM + + + + + + + + + + Device Mgr + + + + Device Mgr + + + + + + + + + + Start Cortex-A + + + + Start Cortex-A + + + + + + + + + + + + + + + + + + + + + + + + + + + Aux F/w + + + + Aux F/w + + + + + + + + + + + start TIFS + + + + start TIFS + + + + + + + + + TIFS + + + + TIFS + + + + + + + + + + Load system config data + + + + Load system config data + + + + + + + + + Start TIFS + + + + Start TIFS + + + + + + + + + Load DM F/w + + + + Load DM F/w + + + + + + + + + + branch + + + + branch + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + TF-A  + + + + TF-A  + + + + + + + + + + OP-TEE + + + + OP-TEE + + + + + + + + + + Cortex A SPL + + + + Cortex A SPL + + + + + + + + + + U-boot + + + + U-boot + + + + + + + + + Load u-boot.img + + + + Load u-boot.img + + + + + + + + + Load Aux core f/w + + +(optional) + + + + Load Aux core f/w(optional) + + + + + + + + + Start Aux core + + +(optional) + + + + Start Aux core(optional) + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + + + + CortexR/M + + +C6x/C7x + + + + CortexR/MC7x/C6x + + + + + + + + + + TIFS/DMSC + + + + TIFS/DMSC + + + + + + + + + + ROM + + + + ROM + + + + + + + + + + Security enclave Boot Processor + + + + Security enclaveProcessor + + + + + + + + + + Boot Loader + + +Processor + + + + Boot LoaderProcessor + + + + + + + + + + Main CPU + + + + Main CPU + + + + + + + + + + Auxiliary + + +Processor + + + + AuxiliaryProcessor + + + + + + + + + + H/w Seq: Reset rls + + + + H/w Seq: Reset rls + + + + + + + + + + Auth tiboot3.bin + + + + Auth tiboot3.bin + + + + + + + + + + Release Reset + + + + Release Reset + + + + + + + + + Cortex-R SPL + + + + Cortex-R SPL + + + + + + + + + Load sysfw.itb + + + + Load sysfw.itb + + + + + + + + + + Auth TIFS + + + + Auth TIFS + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 1cc32a242dde..2659c5ea0dd2 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -34,96 +34,7 @@ Boot Flow: Boot flow is similar to that of AM65x SoC and extending it with remoteproc support. Below is the pictorial representation of boot flow: -.. code-block:: text - - +------------------------------------------------------------------------+-----------------------+ - | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | - +------------------------------------------------------------------------+-----------------------+ - | +--------+ | | | | - | | Reset | | | | | - | +--------+ | | | | - | : | | | | - | +--------+ | +-----------+ | | | - | | *ROM* |----------|-->| Reset rls | | | | - | +--------+ | +-----------+ | | | - | | | | : | | | - | | ROM | | : | | | - | |services| | : | | | - | | | | +-------------+ | | | - | | | | | *R5 ROM* | | | | - | | | | +-------------+ | | | - | | |<---------|---|Load and auth| | | | - | | | | | tiboot3.bin | | | | - | | | | +-------------+ | | | - | | | | : | | | - | | | | : | | | - | | | | : | | | - | | | | +-------------+ | | | - | | | | | *R5 SPL* | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | sysfw.itb | | | | - | | Start | | +-------------+ | | | - | | System |<---------|---| Start | | | | - | |Firmware| | | SYSFW | | | | - | +--------+ | +-------------+ | | | - | : | | | | | | - | +---------+ | | Load | | | | - | | *SYSFW* | | | system | | | | - | +---------+ | | Config data | | | | - | | |<--------|---| | | | | - | | | | +-------------+ | | | - | | | | | DDR | | | | - | | | | | config | | | | - | | | | +-------------+ | | | - | | | | | Load | | | | - | | | | | tispl.bin | | | | - | | | | +-------------+ | | | - | | | | | Load R5 | | | | - | | | | | firmware | | | | - | | | | +-------------+ | | | - | | |<--------|---| Start A72 | | | | - | | | | | and jump to | | | | - | | | | | DM fw image | | | | - | | | | +-------------+ | | | - | | | | | +-----------+ | | - | | |---------|-----------------------|---->| Reset rls | | | - | | | | | +-----------+ | | - | | TIFS | | | : | | - | |Services | | | +-------------+ | | - | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | - | | | | | +-------------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *A72 SPL* | | | - | | | | | +-----------+ | | - | | | | | | Load | | | - | | | | | | u-boot.img| | | - | | | | | +-----------+ | | - | | | | | : | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|---->| *U-Boot* | | | - | | | | | +-----------+ | | - | | | | | | prompt | | | - | | | | | +-----------+ | | - | | | | | | Load R5 | | | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | - | | | | | | Load C6 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C6 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C6 starts | | - | | | | | | Load C7 | | +-----------+ | - | | | | | | Firmware | | | - | | | | | +-----------+ | | - | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | - | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | - | +---------+ | | | +-----------+ | - | | | | | - +------------------------------------------------------------------------+-----------------------+ +.. image:: img/boot_diagram_j721e.svg - Here DMSC acts as master and provides all the critical services. R5/A72 requests DMSC to get these services done as shown in the above diagram. -- 2.40.0