Re: [PATCH] PCI: brcmstb: Avoid downstream access during link training

["Pali Rohár" <pali@kernel.org>]

On Sunday 06 August 2023 06:44:50 Lukas Wunner wrote:
> The Broadcom Set Top Box PCIe controller signals an Asynchronous SError
> Interrupt

This is little incorrect wording. PCIe controller cannot send Async
SError, this is ARMv8 specific thing. In this case PCIe controller is
connected to ARM core via AXI bus and on PCIe transaction timeout it
sends AXI Slave Error, which then ARMv8 core reports to kernel as Async
SError interrupt.

The proper fix is to configure PCIe controller to never send AXI Slave
Error and neither AXI Decode Error (to prevent SErrors at all). For
example Synopsys PCIe controllers have proprietary hidden configuration
bits for enabling/disabling this AXI error reporting behavior.

Or second option is to access affected memory from the ARMv8 core via
synchronous operations and map memory as nGnRnE. Then ARMv8 core reports
AXI Slave Error as Synchronous Abort Exception which you can catch,
examine that was caused on PCIe memory region and fabricate all-ones
response. But the second option is not available for some licensed ARMv8
Cortex cores (e.g. A53) as they do not implement nE (non Early Write
Acknowledgement) memory mapping correctly.

The patch below does not fix the issue at all, instead it opens a new
race condition that if link state is changed _after_ the check and
_before_ accessing config space.

> and thus causes a kernel panic when non-posted transactions
> time out.  This differs from most other PCIe controllers which return a
> fabricated "all ones" response instead.
> 
> To avoid gratuitous kernel panics, the driver reads the link status from
> a proprietary PCIE_MISC_PCIE_STATUS register and skips downstream
> accesses if the link is down.
> 
> However the bits in the proprietary register may purport that the link
> is up even though link training is still in progress (as indicated by
> the Link Training bit in the Link Status register).
> 
> This has been observed with various PCIe switches attached to a BCM2711
> (Raspberry Pi CM4):  The issue is most pronounced with the Pericom
> PI7C9X2G404SV, but has also occasionally been witnessed with the Pericom
> PI7C9X2G404SL and ASMedia ASM1184e.
> 
> Check the Link Training bit in addition to the PCIE_MISC_PCIE_STATUS
> register before performing downstream accesses.
> 
> Signed-off-by: Lukas Wunner <lukas@wunner.de>
> Cc: <stable@vger.kernel.org>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index f593a422bd63..b4abfced8e9b 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -679,8 +679,10 @@ static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
>  	u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
>  	u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
>  	u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
> +	u16 lnksta = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
> +	u16 lt = FIELD_GET(PCI_EXP_LNKSTA_LT, lnksta);
>  
> -	return dla && plu;
> +	return dla && plu && !lt;
>  }
>  
>  static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
> -- 
> 2.39.2
>