Re: CXL Namespaces of ACPI disappearing in Qemu demo

["Yuquan Wang" <wangyuquan1236@phytium.com.cn>]

[-- Attachment #1: Type: text/plain, Size: 1852 bytes --]

Hi, 
On 2023-08-10 21:56,  jonathan.cameron wrote:
 
So took a look at your issue - be it on the cxl-2023-08-07 branch rebased on qemu/master
from today (side effect of looking at the segfault that was stopping me getting to this).
 
For me at least the branch does create an ACPI0017 DSDT entry and an ACPI0016 one
and all the CXL devices turn up in /sys/bus/cxl/devices as expected.
 

Oh, thanks for your guidance. It works so now I can get  ACPI0017 & ACPI0016 information in DSDT.   : )

By the way,  I found that if we add a pcie root port which create the same bus number as we assigned to pxb-cxl, 
the enumeration of cxl and pcie would be different from what we expected.  In this case,  we cannot find 
CXL devices in /sys/bus/cxl/devices. 

According to my test, the error happened in 
"devm_cxl_register_pci_bus()"  of  "add_host_bridge_uport" in  "cxl_acpi_probe".
Actually,  in above case, the incorrect enumeration of pcie will also occur with pxb-pcie except for pxb-cxl, 
hence I guess the kernel did not deal with such case and users just need to avoid it if they need a correct
enumeration result.

My qemu script (which will cause the incorrect enumeration):
qemu-system-x86_64 \
-M q35,nvdimm=on,cxl=on \
-m 4G,maxmem=8G,slots=8 \
-smp 1 \
-object memory-backend-file,id=cxl-mem1,share=on,mem-path=./memfile/cxltest3.raw,size=256M \
-object memory-backend-file,id=cxl-lsa1,share=on,mem-path=./memfile/lsa3.raw,size=256M \
-device ioh3420,bus=pcie.0,id=root_port1,chassis=0,slot=1,addr=04 \
-device qemu-xhci,bus=root_port1 \
-device pxb-cxl,bus_nr=1,bus=pcie.0,id=cxl.1 \
-device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
-device cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
-M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G \
......

Many thanks
Yuquan

[-- Attachment #2: Type: text/html, Size: 3704 bytes --]