From: "Yann E. MORIN" <yann.morin.1998@free.fr>
To: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Conor Dooley <Conor.Dooley@microchip.com>,
Nicolas Ferre <nicolas.ferre@microchip.com>,
Ludovic Desroches <ludovic.desroches@microchip.com>,
buildroot@buildroot.org,
Valentina Fernandez Alanis
<Valentina.FernandezAlanis@microchip.com>,
Jamie Gibbons <jamie.gibbons@microchip.com>
Subject: Re: [Buildroot] [PATCH v2 1/3] arch/Config.in.riscv: update instruction set ext
Date: Wed, 16 Aug 2023 17:04:42 +0200 [thread overview]
Message-ID: <20230816150442.GB1340200@scaer> (raw)
In-Reply-To: <20230816142316.76d45449@windsurf>
Jamie, Thomas, All,
On 2023-08-16 14:23 +0200, Thomas Petazzoni via buildroot spake thusly:
> On Wed, 16 Aug 2023 10:24:37 +0100
> Jamie Gibbons <jamie.gibbons@microchip.com> wrote:
>
> > Allow a RISC-V G core to support C and V. Copy custom RVC and RVV
> > instructions from RISC-V custom core to RISC-V general core.
> >
> > v1 -> v2 changes:
> > - copied RVC and RVV kconfigs to both riscv_g and riscv_custom
>
> We don't want to *copy* them. We want to make them available in both
> cases.
Basically, I think what Thomas expects is something like:
diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 3dfbb4165f..997f7a631d 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -1,26 +1,5 @@
# RISC-V CPU ISA extensions.
-config BR2_RISCV_ISA_RVI
- bool
-
-config BR2_RISCV_ISA_RVM
- bool
-
-config BR2_RISCV_ISA_RVA
- bool
-
-config BR2_RISCV_ISA_RVF
- bool
-
-config BR2_RISCV_ISA_RVD
- bool
-
-config BR2_RISCV_ISA_RVC
- bool
-
-config BR2_RISCV_ISA_RVV
- bool
-
choice
prompt "Target Architecture Variant"
default BR2_riscv_g
@@ -41,38 +20,28 @@ config BR2_riscv_custom
endchoice
-if BR2_riscv_custom
-
comment "Instruction Set Extensions"
-config BR2_RISCV_ISA_CUSTOM_RVM
+config BR2_RISCV_ISA_RVM
bool "Integer Multiplication and Division (M)"
- select BR2_RISCV_ISA_RVM
-config BR2_RISCV_ISA_CUSTOM_RVA
+config BR2_RISCV_ISA_RVA
bool "Atomic Instructions (A)"
- select BR2_RISCV_ISA_RVA
-config BR2_RISCV_ISA_CUSTOM_RVF
+config BR2_RISCV_ISA_RVF
bool "Single-precision Floating-point (F)"
- select BR2_RISCV_ISA_RVF
-config BR2_RISCV_ISA_CUSTOM_RVD
+config BR2_RISCV_ISA_RVD
bool "Double-precision Floating-point (D)"
depends on BR2_RISCV_ISA_RVF
- select BR2_RISCV_ISA_RVD
-config BR2_RISCV_ISA_CUSTOM_RVC
+config BR2_RISCV_ISA_RVC
bool "Compressed Instructions (C)"
- select BR2_RISCV_ISA_RVC
-config BR2_RISCV_ISA_CUSTOM_RVV
+config BR2_RISCV_ISA_RVV
bool "Vector Instructions (V)"
- select BR2_RISCV_ISA_RVV
select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
-endif
-
choice
prompt "Target Architecture Size"
default BR2_RISCV_64
Thomas?
Regards,
Yann E. MORIN.
> Also, the changelog shouldn't go inside the commit log but...
>
> >
> > Signed-off-by: Jamie Gibbons <jamie.gibbons@microchip.com>
> > ---
>
> ... here, after the "---" line.
>
> Thanks!
>
> Thomas
> --
> Thomas Petazzoni, co-owner and CEO, Bootlin
> Embedded Linux and Kernel engineering and training
> https://bootlin.com
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot
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next prev parent reply other threads:[~2023-08-16 15:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-16 9:24 [Buildroot] [PATCH v2 0/3] Update RISC-V Instruction Sets Jamie Gibbons via buildroot
2023-08-16 9:24 ` [Buildroot] [PATCH v2 1/3] arch/Config.in.riscv: update instruction set ext Jamie Gibbons via buildroot
2023-08-16 12:23 ` Thomas Petazzoni via buildroot
2023-08-16 15:04 ` Yann E. MORIN [this message]
2023-08-17 7:40 ` Thomas Petazzoni via buildroot
2023-08-17 8:27 ` yann.morin
2023-08-17 9:45 ` Thomas Petazzoni via buildroot
2023-08-16 9:24 ` [Buildroot] [PATCH v2 2/3] configs/microchip_mpfs_icicle_defconfig: update instruction sets Jamie Gibbons via buildroot
2023-08-16 9:24 ` [Buildroot] [PATCH v2 3/3] board/microchip/mpfs_icicle: update post-image script Jamie Gibbons via buildroot
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