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charset=us-ascii Content-Disposition: inline tree: https://github.com/intel/linux-intel-lts.git 6.1/linux head: 1250fc0938619046c0d5513aae318293a0563282 commit: c0af7a876be298ceb17ab83c5fbb3c0ab0251beb [907/2351] drm/amdgpu: Move to common indirect reg access helper config: x86_64-randconfig-x004-20230817 (https://download.01.org/0day-ci/archive/20230817/202308172018.hJT8s8FR-lkp@intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce: (https://download.01.org/0day-ci/archive/20230817/202308172018.hJT8s8FR-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202308172018.hJT8s8FR-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:758: warning: Excess function parameter 'pcie_index' description in 'amdgpu_device_indirect_wreg' >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:758: warning: Excess function parameter 'pcie_data' description in 'amdgpu_device_indirect_wreg' >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:789: warning: Excess function parameter 'pcie_index' description in 'amdgpu_device_indirect_wreg64' >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:789: warning: Excess function parameter 'pcie_data' description in 'amdgpu_device_indirect_wreg64' drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:5195: warning: Function parameter or member 'reset_context' not described in 'amdgpu_device_gpu_recover' vim +758 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 1bba36834c3bc3 Hawking Zhang 2020-09-17 745 1bba36834c3bc3 Hawking Zhang 2020-09-17 746 /** 1bba36834c3bc3 Hawking Zhang 2020-09-17 747 * amdgpu_device_indirect_wreg - write an indirect register address 1bba36834c3bc3 Hawking Zhang 2020-09-17 748 * 1bba36834c3bc3 Hawking Zhang 2020-09-17 749 * @adev: amdgpu_device pointer 1bba36834c3bc3 Hawking Zhang 2020-09-17 750 * @pcie_index: mmio register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 751 * @pcie_data: mmio register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 752 * @reg_addr: indirect register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 753 * @reg_data: indirect register data 1bba36834c3bc3 Hawking Zhang 2020-09-17 754 * 1bba36834c3bc3 Hawking Zhang 2020-09-17 755 */ 1bba36834c3bc3 Hawking Zhang 2020-09-17 756 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1bba36834c3bc3 Hawking Zhang 2020-09-17 757 u32 reg_addr, u32 reg_data) 1bba36834c3bc3 Hawking Zhang 2020-09-17 @758 { c0af7a876be298 Hawking Zhang 2023-03-06 759 unsigned long flags, pcie_index, pcie_data; 1bba36834c3bc3 Hawking Zhang 2020-09-17 760 void __iomem *pcie_index_offset; 1bba36834c3bc3 Hawking Zhang 2020-09-17 761 void __iomem *pcie_data_offset; 1bba36834c3bc3 Hawking Zhang 2020-09-17 762 c0af7a876be298 Hawking Zhang 2023-03-06 763 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); c0af7a876be298 Hawking Zhang 2023-03-06 764 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); c0af7a876be298 Hawking Zhang 2023-03-06 765 1bba36834c3bc3 Hawking Zhang 2020-09-17 766 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1bba36834c3bc3 Hawking Zhang 2020-09-17 767 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 1bba36834c3bc3 Hawking Zhang 2020-09-17 768 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 1bba36834c3bc3 Hawking Zhang 2020-09-17 769 1bba36834c3bc3 Hawking Zhang 2020-09-17 770 writel(reg_addr, pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 771 readl(pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 772 writel(reg_data, pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 773 readl(pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 774 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1bba36834c3bc3 Hawking Zhang 2020-09-17 775 } 1bba36834c3bc3 Hawking Zhang 2020-09-17 776 1bba36834c3bc3 Hawking Zhang 2020-09-17 777 /** 1bba36834c3bc3 Hawking Zhang 2020-09-17 778 * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address 1bba36834c3bc3 Hawking Zhang 2020-09-17 779 * 1bba36834c3bc3 Hawking Zhang 2020-09-17 780 * @adev: amdgpu_device pointer 1bba36834c3bc3 Hawking Zhang 2020-09-17 781 * @pcie_index: mmio register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 782 * @pcie_data: mmio register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 783 * @reg_addr: indirect register offset 1bba36834c3bc3 Hawking Zhang 2020-09-17 784 * @reg_data: indirect register data 1bba36834c3bc3 Hawking Zhang 2020-09-17 785 * 1bba36834c3bc3 Hawking Zhang 2020-09-17 786 */ 1bba36834c3bc3 Hawking Zhang 2020-09-17 787 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1bba36834c3bc3 Hawking Zhang 2020-09-17 788 u32 reg_addr, u64 reg_data) 1bba36834c3bc3 Hawking Zhang 2020-09-17 @789 { c0af7a876be298 Hawking Zhang 2023-03-06 790 unsigned long flags, pcie_index, pcie_data; 1bba36834c3bc3 Hawking Zhang 2020-09-17 791 void __iomem *pcie_index_offset; 1bba36834c3bc3 Hawking Zhang 2020-09-17 792 void __iomem *pcie_data_offset; 1bba36834c3bc3 Hawking Zhang 2020-09-17 793 c0af7a876be298 Hawking Zhang 2023-03-06 794 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); c0af7a876be298 Hawking Zhang 2023-03-06 795 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); c0af7a876be298 Hawking Zhang 2023-03-06 796 1bba36834c3bc3 Hawking Zhang 2020-09-17 797 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1bba36834c3bc3 Hawking Zhang 2020-09-17 798 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 1bba36834c3bc3 Hawking Zhang 2020-09-17 799 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 1bba36834c3bc3 Hawking Zhang 2020-09-17 800 1bba36834c3bc3 Hawking Zhang 2020-09-17 801 /* write low 32 bits */ 1bba36834c3bc3 Hawking Zhang 2020-09-17 802 writel(reg_addr, pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 803 readl(pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 804 writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 805 readl(pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 806 /* write high 32 bits */ 1bba36834c3bc3 Hawking Zhang 2020-09-17 807 writel(reg_addr + 4, pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 808 readl(pcie_index_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 809 writel((u32)(reg_data >> 32), pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 810 readl(pcie_data_offset); 1bba36834c3bc3 Hawking Zhang 2020-09-17 811 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1bba36834c3bc3 Hawking Zhang 2020-09-17 812 } 1bba36834c3bc3 Hawking Zhang 2020-09-17 813 :::::: The code at line 758 was first introduced by commit :::::: 1bba36834c3bc317d8a30dd5d0cc3e59d64dbfb3 drm/amdgpu: add helper function for indirect reg access (v3) :::::: TO: Hawking Zhang :::::: CC: Alex Deucher -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki