All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Huacai Chen" <chenhuacai@loongson.cn>,
	"Xiaojuan Yang" <yangxiaojuan@loongson.cn>,
	"Alex Bennée" <alex.bennee@linaro.org>, "Jiajie Chen" <c@jia.je>,
	"Song Gao" <gaosong@loongson.cn>
Subject: [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers
Date: Fri, 18 Aug 2023 19:20:09 +0200	[thread overview]
Message-ID: <20230818172016.24504-2-philmd@linaro.org> (raw)
In-Reply-To: <20230818172016.24504-1-philmd@linaro.org>

Various CSR registers have Read/Write fields. We might
want to see guest trying to change such registers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/loongarch/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..7107968699 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -544,6 +544,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
 static void loongarch_qemu_write(void *opaque, hwaddr addr,
                                  uint64_t val, unsigned size)
 {
+    qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n",
+                  __func__, addr);
 }
 
 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
-- 
2.41.0



  reply	other threads:[~2023-08-18 17:20 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-18 17:20 [PATCH v2 0/8] target/loongarch: Cleanups in preparation of loongarch32 support Philippe Mathieu-Daudé
2023-08-18 17:20 ` Philippe Mathieu-Daudé [this message]
2023-08-19  7:33   ` [PATCH v2 1/8] target/loongarch: Log I/O write accesses to CSR registers gaosong
2023-08-18 17:20 ` [PATCH v2 2/8] target/loongarch: Remove duplicated disas_set_info assignment Philippe Mathieu-Daudé
2023-08-19  7:34   ` gaosong
2023-08-18 17:20 ` [PATCH v2 3/8] target/loongarch: Fix loongarch_la464_initfn() misses setting LSPW Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 4/8] target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPU Philippe Mathieu-Daudé
2023-08-18 17:33   ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init Philippe Mathieu-Daudé
2023-08-18 17:32   ` Richard Henderson
2023-08-18 17:20 ` [PATCH v2 6/8] target/loongarch: Add function to check current arch Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 7/8] target/loongarch: Add new object class for loongarch32 cpus Philippe Mathieu-Daudé
2023-08-18 17:20 ` [PATCH v2 8/8] target/loongarch: Add GDB support for loongarch32 mode Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230818172016.24504-2-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=c@jia.je \
    --cc=chenhuacai@loongson.cn \
    --cc=gaosong@loongson.cn \
    --cc=qemu-devel@nongnu.org \
    --cc=yangxiaojuan@loongson.cn \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.