Re: [PATCH v2 03/15] drm/panthor: Add GPU register definitions

[Boris Brezillon <boris.brezillon@collabora.com>]

On Fri, 11 Aug 2023 15:13:23 +0100
Steven Price <steven.price@arm.com> wrote:

> > +#define AS_TRANSCFG_LO(as)				(MMU_AS(as) + 0x30)
> > +#define AS_TRANSCFG_HI(as)				(MMU_AS(as) + 0x34)
> > +#define   AS_TRANSCFG_ADRMODE_LEGACY			(0 << 0)  
> 
> I don't believe legacy mode exists any more (it's not in my copy of the
> spec).

Oops, I'll drop it.

> 
> > +#define   AS_TRANSCFG_ADRMODE_UNMAPPED			(1 << 0)
> > +#define   AS_TRANSCFG_ADRMODE_IDENTITY			(2 << 0)
> > +#define   AS_TRANSCFG_ADRMODE_AARCH64_4K		(6 << 0)
> > +#define   AS_TRANSCFG_ADRMODE_AARCH64_64K		(8 << 0)
> > +#define   AS_TRANSCFG_INA_BITS(x)			((x) << 6)
> > +#define   AS_TRANSCFG_OUTA_BITS(x)			((x) << 14)
> > +#define   AS_TRANSCFG_SL_CONCAT				BIT(22)
> > +#define   AS_TRANSCFG_PTW_MEMATTR_NC			(1 << 24)
> > +#define   AS_TRANSCFG_PTW_MEMATTR_WB			(2 << 24)
> > +#define   AS_TRANSCFG_PTW_SH_NS				(0 << 28)
> > +#define   AS_TRANSCFG_PTW_SH_OS				(2 << 28)
> > +#define   AS_TRANSCFG_PTW_SH_IS				(3 << 28)
> > +#define   AS_TRANSCFG_PTW_RA				BIT(30)
> > +#define   AS_TRANSCFG_DISABLE_HIER_AP			BIT(33)
> > +#define   AS_TRANSCFG_DISABLE_AF_FAULT			BIT(34)
> > +#define   AS_TRANSCFG_WXN				BIT(35)
> > +#define   AS_TRANSCFG_XREADABLE				BIT(36)
> > +#define AS_FAULTEXTRA_LO(as)				(MMU_AS(as) + 0x38)
> > +#define AS_FAULTEXTRA_HI(as)				(MMU_AS(as) + 0x3C)
> > +
> > +#define CSF_GPU_LATEST_FLUSH_ID				0x10000
> > +#define CSF_GPU_LATEST_FLUSH_ID_DEFAULT			0xffffe0  
> 
> I'm not sure why we need the default value of this register? Seems an
> odd thing to include.

I'm using it to set the dummy FLUSH_ID page to the reset value on
suspend, which you suggested to set to zero or one. If we agree on that
(still want to explain the reasoning before taking a decision), I'll
drop this definition.

> 
> Steve
> 
> > +
> > +#define CSF_DOORBELL(i)					(0x80000 + ((i) * 0x10000))
> > +#define CSF_GLB_DOORBELL_ID				0
> > +
> > +#define gpu_write(dev, reg, data) \
> > +	writel(data, (dev)->iomem + (reg))
> > +
> > +#define gpu_read(dev, reg) \
> > +	readl((dev)->iomem + (reg))
> > +
> > +#endif  
>