[pci:controller/qcom-ep 3/3] drivers/pci/controller/dwc/pcie-qcom-ep.c:198: warning: Function parameter or member 'icc_mem' not described in 'qcom_pcie_ep'

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git controller/qcom-ep
head:   0c104996e6a856536e311c6fee66d8099c5c6c7b
commit: 0c104996e6a856536e311c6fee66d8099c5c6c7b [3/3] PCI: qcom-ep: Add ICC bandwidth voting support
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20230829/202308292252.HNCCTM4u-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230829/202308292252.HNCCTM4u-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308292252.HNCCTM4u-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-qcom-ep.c:198: warning: Function parameter or member 'icc_mem' not described in 'qcom_pcie_ep'


vim +198 drivers/pci/controller/dwc/pcie-qcom-ep.c

f55fee56a63103 Manivannan Sadhasivam     2021-09-20  150  
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  151  /**
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  152   * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  153   * @pci: Designware PCIe controller struct
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  154   * @parf: Qualcomm PCIe specific PARF register base
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  155   * @elbi: Designware PCIe specific ELBI register base
6dbba2b53c3bcb Manivannan Sadhasivam     2022-09-14  156   * @mmio: MMIO register base
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  157   * @perst_map: PERST regmap
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  158   * @mmio_res: MMIO region resource
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  159   * @core_reset: PCIe Endpoint core reset
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  160   * @reset: PERST# GPIO
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  161   * @wake: WAKE# GPIO
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  162   * @phy: PHY controller block
6dbba2b53c3bcb Manivannan Sadhasivam     2022-09-14  163   * @debugfs: PCIe Endpoint Debugfs directory
e2efd31465b1d9 Manivannan Sadhasivam     2022-09-14  164   * @clks: PCIe clocks
e2efd31465b1d9 Manivannan Sadhasivam     2022-09-14  165   * @num_clks: PCIe clocks count
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  166   * @perst_en: Flag for PERST enable
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  167   * @perst_sep_en: Flag for PERST separation enable
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  168   * @link_status: PCIe Link status
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  169   * @global_irq: Qualcomm PCIe specific Global IRQ
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  170   * @perst_irq: PERST# IRQ
f1bfbd000f3bc4 Manivannan Sadhasivam     2022-09-14  171   */
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  172  struct qcom_pcie_ep {
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  173  	struct dw_pcie pci;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  174  
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  175  	void __iomem *parf;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  176  	void __iomem *elbi;
6dbba2b53c3bcb Manivannan Sadhasivam     2022-09-14  177  	void __iomem *mmio;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  178  	struct regmap *perst_map;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  179  	struct resource *mmio_res;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  180  
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  181  	struct reset_control *core_reset;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  182  	struct gpio_desc *reset;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  183  	struct gpio_desc *wake;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  184  	struct phy *phy;
6dbba2b53c3bcb Manivannan Sadhasivam     2022-09-14  185  	struct dentry *debugfs;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  186  
0c104996e6a856 Krishna chaitanya chundru 2023-07-19  187  	struct icc_path *icc_mem;
0c104996e6a856 Krishna chaitanya chundru 2023-07-19  188  
e2efd31465b1d9 Manivannan Sadhasivam     2022-09-14  189  	struct clk_bulk_data *clks;
e2efd31465b1d9 Manivannan Sadhasivam     2022-09-14  190  	int num_clks;
e2efd31465b1d9 Manivannan Sadhasivam     2022-09-14  191  
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  192  	u32 perst_en;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  193  	u32 perst_sep_en;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  194  
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  195  	enum qcom_pcie_ep_link_status link_status;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  196  	int global_irq;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  197  	int perst_irq;
f55fee56a63103 Manivannan Sadhasivam     2021-09-20 @198  };
f55fee56a63103 Manivannan Sadhasivam     2021-09-20  199  

:::::: The code at line 198 was first introduced by commit
:::::: f55fee56a631032969480e4b0ee5d79734fe3c69 PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver

:::::: TO: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>

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