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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Terry Bowman <terry.bowman@amd.com>, <alison.schofield@intel.com>,
	<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
	<bwidawsk@kernel.org>, <dan.j.williams@intel.com>,
	<dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings
Date: Fri, 1 Sep 2023 10:06:54 +0100	[thread overview]
Message-ID: <20230901100654.00006799@Huawei.com> (raw)
In-Reply-To: <ZPCGCwakf3BeV7gp@rric.localdomain>

On Thu, 31 Aug 2023 14:22:35 +0200
Robert Richter <rrichter@amd.com> wrote:

> On 29.08.23 14:38:51, Jonathan Cameron wrote:
> > On Fri, 25 Aug 2023 18:31:57 -0500
> > Terry Bowman <terry.bowman@amd.com> wrote:
> >   
> > > From: Robert Richter <rrichter@amd.com>  
> > 
> > Hi Robert, Terry,
> >   
> > > 
> > > The component registers of a component may not exist or are not
> > > needed.  
> > 
> > How do we now it's not needed in this function?
> > Perhaps "may not exist." is the bit that matters in this sentence.
> >   
> > > The setup may fail for that reason. In some cases the
> > > initialization should continue anyway. Thus, always initialize struct
> > > cxl_register_map with valid values. In case of errors, zero it, set a
> > > value for @dev and make @resource a the valid value using  
> > 
> > make @resource CXL_RESOURCE_NONE.
> > 
> > (not "a the")
> >   
> > > CXL_RESOURCE_NONE.  
> > 
> > It might be worth making it clear that this will (I think) only matter
> > for future usecases and isn't a fix for how this function is used today.  
> 
> I reworded the whole text:
> 
> """
> The component registers of a component may not exist and
> cxl_setup_comp_regs() will fail for that reason. In another case,
> Software may not use and set those registers up. cxl_setup_comp_regs()
> is then called with a base address of CXL_RESOURCE_NONE. Both are
> valid cases, but the function returns without initializing the
> register map.
> 
> Now, a missing component register block is not necessarily a reason to
> fail (feature is optional or its existence checked later). Change
> cxl_setup_comp_regs() to also use components with the component
> register block missing. Thus, always initialize struct
> cxl_register_map with valid values, set @dev and make @resource
> CXL_RESOURCE_NONE.
> 
> The change is in preparation of follow-on patches.
> """

Looks good to me.

J
> 
> I hope that is better now.
> 
> >   
> > > 
> > > Signed-off-by: Robert Richter <rrichter@amd.com>
> > > Signed-off-by: Terry Bowman <terry.bowman@amd.com>  
> > Otherwise seems sensible to me with one comment below.
> > 
> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >   
> > > ---
> > >  drivers/cxl/core/port.c | 11 ++++++-----
> > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> > > index 724be8448eb4..2d22e7a5629b 100644
> > > --- a/drivers/cxl/core/port.c
> > > +++ b/drivers/cxl/core/port.c
> > > @@ -693,16 +693,17 @@ static struct cxl_port *cxl_port_alloc(struct device *uport_dev,
> > >  static int cxl_setup_comp_regs(struct device *dev, struct cxl_register_map *map,
> > >  			       resource_size_t component_reg_phys)
> > >  {
> > > -	if (component_reg_phys == CXL_RESOURCE_NONE)
> > > -		return 0;
> > > -
> > >  	*map = (struct cxl_register_map) {
> > >  		.dev = dev,
> > > -		.reg_type = CXL_REGLOC_RBI_COMPONENT,  
> > 
> > Could set this explicitly to CXL_REGLOC_RBI_EMPTY
> > which is what happens anyway, but it isn't obvious that
> > 0 maps to something that indicates this doesn't exist.  
> 
> Will change that.
> 
> Thanks,
> 
> -Robert
> 
> 
> >   
> > >  		.resource = component_reg_phys,
> > > -		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,
> > >  	};
> > >  
> > > +	if (component_reg_phys == CXL_RESOURCE_NONE)
> > > +		return 0;
> > > +
> > > +	map->reg_type = CXL_REGLOC_RBI_COMPONENT;
> > > +	map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE;
> > > +
> > >  	return cxl_setup_regs(map);
> > >  }
> > >    
> >   


  reply	other threads:[~2023-09-01  9:07 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-25 23:31 [PATCH v9 00/15] cxl/pci: Add support for RCH RAS error handling Terry Bowman
2023-08-25 23:31 ` [PATCH v9 01/15] cxl/port: Pre-initialize component register mappings Terry Bowman
2023-08-29 13:38   ` Jonathan Cameron
2023-08-31 12:22     ` Robert Richter
2023-09-01  9:06       ` Jonathan Cameron [this message]
2023-08-25 23:31 ` [PATCH v9 02/15] cxl/regs: Prepare for multiple users of " Terry Bowman
2023-08-29 13:52   ` Jonathan Cameron
2023-08-31 12:43     ` Robert Richter
2023-09-01  9:08       ` Jonathan Cameron
2023-08-31 18:11   ` Dan Williams
2023-09-01  9:10     ` Jonathan Cameron
2023-08-25 23:31 ` [PATCH v9 03/15] cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 04/15] cxl/hdm: Use stored Component Register mappings to map HDM decoder capability Terry Bowman
2023-08-25 23:32 ` [PATCH v9 05/15] cxl/pci: Remove Component Register base address from struct cxl_dev_state Terry Bowman
2023-08-25 23:32 ` [PATCH v9 06/15] cxl/port: Remove Component Register base address from struct cxl_port Terry Bowman
2023-08-25 23:32 ` [PATCH v9 07/15] cxl/pci: Add RCH downstream port AER register discovery Terry Bowman
2023-08-25 23:32 ` [PATCH v9 08/15] PCI/AER: Refactor cper_print_aer() for use by CXL driver module Terry Bowman
2023-08-25 23:32 ` [PATCH v9 09/15] cxl/pci: Update CXL error logging to use RAS register address Terry Bowman
2023-08-25 23:32 ` [PATCH v9 10/15] cxl/pci: Map RCH downstream AER registers for logging protocol errors Terry Bowman
2023-08-25 23:32 ` [PATCH v9 11/15] cxl/pci: Add RCH downstream port error logging Terry Bowman
2023-08-25 23:32 ` [PATCH v9 12/15] cxl/pci: Disable root port interrupts in RCH mode Terry Bowman
2023-08-25 23:32 ` [PATCH v9 13/15] PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler Terry Bowman
2023-08-25 23:32   ` Terry Bowman
2023-08-25 23:32 ` [PATCH v9 14/15] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Terry Bowman
2023-08-25 23:32 ` [PATCH v9 15/15] cxl/core/regs: Rename phys_addr in cxl_map_component_regs() Terry Bowman
2023-08-29 13:54   ` Jonathan Cameron

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