From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B56AEEEB566 for ; Fri, 8 Sep 2023 19:31:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2941810E922; Fri, 8 Sep 2023 19:31:08 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5562F10E932; Fri, 8 Sep 2023 19:31:05 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 151A1B821E2; Fri, 8 Sep 2023 19:31:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77506C4339A; Fri, 8 Sep 2023 19:31:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694201463; bh=FNhRXj0vE4XTs9u78Jg7KGumTQtffqkpeiDGPEe1NNU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEUXji/JAFMckijVjCfmxeZPzD7jsDvcDL4mnw5C/x+dR1cLe+7N7V0o+8ROjmuSB eFRZrp839ipeD8rLh9kvMS6yh9UyVVgdMV7nMQybbFbKiI3jIZtkWo+dVDPb4W0G6Q 0WRAUNYmLbAWIQQFX/8t/T+wDKHZj+oJBm03lRRI3mX5+49nRCL8RIRPMoC8AIDnPD mX8QcmCxNvkWvzZOpDtdzhZjb2Eg3Fn2zZpO5dGpQ6f9OyzJYc5cuP+BeyjCcTDeHx Q6JYbQPAGFL0E5G9IxCe5Y4f0B3yVbF222QkhSMWrZPVyD1XOUcoX+NPYF5phZGCiQ UAA50flPIy2oQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 6.5 23/36] drm/amd/display: Use max memclk variable when setting max memclk Date: Fri, 8 Sep 2023 15:28:34 -0400 Message-Id: <20230908192848.3462476-23-sashal@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230908192848.3462476-1-sashal@kernel.org> References: <20230908192848.3462476-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.5.2 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Dillon.Varone@amd.com, Chris.Park@amd.com, Tom Chung , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, sunpeng.li@amd.com, airlied@gmail.com, qingqing.zhuo@amd.com, Xinhui.Pan@amd.com, Rodrigo.Siqueira@amd.com, Samson Tam , wenjing.liu@amd.com, Daniel Wheeler , aurabindo.pillai@amd.com, Alvin Lee , daniel@ffwll.ch, Alex Deucher , jun.lei@amd.com, harry.wentland@amd.com, christian.koenig@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Alvin Lee [ Upstream commit 2b1b838ea8e5437ef06a29818d16e9efdfaf0037 ] [Description] In overclocking scenarios the max memclk could be higher than the DC mode limit. However, for configs that don't support MCLK switching we need to set the max memclk to the overclocked max instead of the DC mode max or we could result in underflow. Reviewed-by: Samson Tam Acked-by: Tom Chung Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index cb992aca760dc..5fc78bf927bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -802,7 +802,7 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); + clk_mgr_base->bw_params->max_memclk_mhz); } else { dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); -- 2.40.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03A50EEB56B for ; Fri, 8 Sep 2023 19:31:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229437AbjIHTbz (ORCPT ); Fri, 8 Sep 2023 15:31:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344842AbjIHTbx (ORCPT ); Fri, 8 Sep 2023 15:31:53 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB0BD211D; Fri, 8 Sep 2023 12:31:27 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77506C4339A; Fri, 8 Sep 2023 19:31:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694201463; bh=FNhRXj0vE4XTs9u78Jg7KGumTQtffqkpeiDGPEe1NNU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEUXji/JAFMckijVjCfmxeZPzD7jsDvcDL4mnw5C/x+dR1cLe+7N7V0o+8ROjmuSB eFRZrp839ipeD8rLh9kvMS6yh9UyVVgdMV7nMQybbFbKiI3jIZtkWo+dVDPb4W0G6Q 0WRAUNYmLbAWIQQFX/8t/T+wDKHZj+oJBm03lRRI3mX5+49nRCL8RIRPMoC8AIDnPD mX8QcmCxNvkWvzZOpDtdzhZjb2Eg3Fn2zZpO5dGpQ6f9OyzJYc5cuP+BeyjCcTDeHx Q6JYbQPAGFL0E5G9IxCe5Y4f0B3yVbF222QkhSMWrZPVyD1XOUcoX+NPYF5phZGCiQ UAA50flPIy2oQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Alvin Lee , Samson Tam , Tom Chung , Daniel Wheeler , Alex Deucher , Sasha Levin , harry.wentland@amd.com, sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, jun.lei@amd.com, qingqing.zhuo@amd.com, Dillon.Varone@amd.com, aurabindo.pillai@amd.com, wenjing.liu@amd.com, Chris.Park@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.5 23/36] drm/amd/display: Use max memclk variable when setting max memclk Date: Fri, 8 Sep 2023 15:28:34 -0400 Message-Id: <20230908192848.3462476-23-sashal@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230908192848.3462476-1-sashal@kernel.org> References: <20230908192848.3462476-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.5.2 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Alvin Lee [ Upstream commit 2b1b838ea8e5437ef06a29818d16e9efdfaf0037 ] [Description] In overclocking scenarios the max memclk could be higher than the DC mode limit. However, for configs that don't support MCLK switching we need to set the max memclk to the overclocked max instead of the DC mode max or we could result in underflow. Reviewed-by: Samson Tam Acked-by: Tom Chung Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index cb992aca760dc..5fc78bf927bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -802,7 +802,7 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); + clk_mgr_base->bw_params->max_memclk_mhz); } else { dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); -- 2.40.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6C58EEB56B for ; Fri, 8 Sep 2023 19:31:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6033210E1DE; Fri, 8 Sep 2023 19:31:08 +0000 (UTC) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5562F10E932; Fri, 8 Sep 2023 19:31:05 +0000 (UTC) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 151A1B821E2; Fri, 8 Sep 2023 19:31:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77506C4339A; Fri, 8 Sep 2023 19:31:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694201463; bh=FNhRXj0vE4XTs9u78Jg7KGumTQtffqkpeiDGPEe1NNU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEUXji/JAFMckijVjCfmxeZPzD7jsDvcDL4mnw5C/x+dR1cLe+7N7V0o+8ROjmuSB eFRZrp839ipeD8rLh9kvMS6yh9UyVVgdMV7nMQybbFbKiI3jIZtkWo+dVDPb4W0G6Q 0WRAUNYmLbAWIQQFX/8t/T+wDKHZj+oJBm03lRRI3mX5+49nRCL8RIRPMoC8AIDnPD mX8QcmCxNvkWvzZOpDtdzhZjb2Eg3Fn2zZpO5dGpQ6f9OyzJYc5cuP+BeyjCcTDeHx Q6JYbQPAGFL0E5G9IxCe5Y4f0B3yVbF222QkhSMWrZPVyD1XOUcoX+NPYF5phZGCiQ UAA50flPIy2oQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH AUTOSEL 6.5 23/36] drm/amd/display: Use max memclk variable when setting max memclk Date: Fri, 8 Sep 2023 15:28:34 -0400 Message-Id: <20230908192848.3462476-23-sashal@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230908192848.3462476-1-sashal@kernel.org> References: <20230908192848.3462476-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.5.2 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sasha Levin , Dillon.Varone@amd.com, Chris.Park@amd.com, Tom Chung , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, sunpeng.li@amd.com, qingqing.zhuo@amd.com, Xinhui.Pan@amd.com, Rodrigo.Siqueira@amd.com, Samson Tam , wenjing.liu@amd.com, Daniel Wheeler , aurabindo.pillai@amd.com, Alvin Lee , Alex Deucher , jun.lei@amd.com, christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alvin Lee [ Upstream commit 2b1b838ea8e5437ef06a29818d16e9efdfaf0037 ] [Description] In overclocking scenarios the max memclk could be higher than the DC mode limit. However, for configs that don't support MCLK switching we need to set the max memclk to the overclocked max instead of the DC mode max or we could result in underflow. Reviewed-by: Samson Tam Acked-by: Tom Chung Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index cb992aca760dc..5fc78bf927bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -802,7 +802,7 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); else dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, - clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); + clk_mgr_base->bw_params->max_memclk_mhz); } else { dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); -- 2.40.1