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From: Conor Dooley <conor.dooley@microchip.com>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	<linux-riscv@lists.infradead.org>
Subject: more RELOCATABLE + errata code model issues
Date: Mon, 18 Sep 2023 11:36:03 +0100	[thread overview]
Message-ID: <20230918-retool-presoak-e47ed2f2b8d3@wendy> (raw)


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Hey Alex,

LKP reported [1] some issues with relocatable kernels & code models.
You didn't touch the commit that caused the issues, so you didn't see
the failure report I guess, but Prabhakar is looking for some guidance
on what he should do to resolve the problems. Copy-pasting from his
mail:
> > All errors (new ones prefixed by >>):
> > 
> > >> ld.lld: error: relocation R_RISCV_LO12_I cannot be used against
> > >> symbol 'riscv_cbom_block_size'; recompile with -fPIC
> >    >>> defined in vmlinux.a(arch/riscv/mm/cacheflush.o)
> >    >>> referenced by errata.c
> >    >>>               arch/riscv/errata/andes/errata.o:(andes_errata_patch_func) in archive vmlinux.a
> > 
> I did reproduce this issue locally. The andes errata is not compiled as medany. The config is RELOCATABLE + MEDLOW. I can see the cacheflush.o is compiled with medany flag.
> I can fix the build by adding a medany flag as below:
> +#ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
> +CFLAGS_errata.o := -mcmodel=medany
> #endif
> 
> But I am not sure if this is correct approach. Any pointers on this?

The T-Head errata have something similar, so seems like fair game to me.
Any thoughts?

Thanks,
Conor.

[1] - https://lore.kernel.org/all/202309111311.8tcq3KVc-lkp@intel.com/

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             reply	other threads:[~2023-09-18 10:36 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-18 10:36 Conor Dooley [this message]
2023-09-18 15:15 ` more RELOCATABLE + errata code model issues Palmer Dabbelt
2023-09-18 16:59   ` Alexandre Ghiti

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