From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9201DCD5BD0 for ; Tue, 19 Sep 2023 14:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233022AbjISO7f (ORCPT ); Tue, 19 Sep 2023 10:59:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232987AbjISO7d (ORCPT ); Tue, 19 Sep 2023 10:59:33 -0400 Received: from bmailout3.hostsharing.net (bmailout3.hostsharing.net [176.9.242.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 231F4185 for ; Tue, 19 Sep 2023 07:59:23 -0700 (PDT) Received: from h08.hostsharing.net (h08.hostsharing.net [IPv6:2a01:37:1000::53df:5f1c:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "*.hostsharing.net", Issuer "RapidSSL Global TLS RSA4096 SHA256 2022 CA1" (verified OK)) by bmailout3.hostsharing.net (Postfix) with ESMTPS id 681E0103201BB; Tue, 19 Sep 2023 16:59:21 +0200 (CEST) Received: by h08.hostsharing.net (Postfix, from userid 100393) id 3A4AD517D5; Tue, 19 Sep 2023 16:59:21 +0200 (CEST) Date: Tue, 19 Sep 2023 16:59:21 +0200 From: Lukas Wunner To: "Schroeder, Chad" Cc: "bhelgaas@google.com" , "linux-pci@vger.kernel.org" Subject: Re: PCIe device issue since v6.1.16 Message-ID: <20230919145921.GA8609@wunner.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Chad, On Tue, Sep 19, 2023 at 02:17:29PM +0000, Schroeder, Chad wrote: > After researching the issue, I found the commit that lead system error: > > https://lore.kernel.org/all/da77c92796b99ec568bd070cbe4725074a117038.1673769517.git.lukas@wunner.de/ > > Specifically, this removal: > > - Drop an unnecessary 1 sec delay from pci_reset_secondary_bus() which > is now performed by pci_bridge_wait_for_secondary_bus(). A static > delay this long is only necessary for Conventional PCI, so modern > PCIe systems benefit from shorter reset times as a side effect. Thanks for the report and sorry for the breakage. This endpoint device only supports Gen1 speed (2.5GT/s) and does not support Data Link Layer Link Active Reporting. I have a suspicion that I neglected to take this case into account in pci_bridge_wait_for_secondary_bus(). To better understand what's going on, could you also provide "lspci -vvv" output of the parent bridge above 0000:65:00.0 (i.e. of the bridge whose secondary bus is 65)? Thanks! Lukas