From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
devicetree@vger.kernel.org,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@rivosinc.com>,
linux-kernel@vger.kernel.org, Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v9 01/15] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Thu, 28 Sep 2023 11:41:53 +0530 [thread overview]
Message-ID: <20230928061207.1841513-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com>
The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:
[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().
Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
*/
int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
{
- int rc;
-
for (; node; node = node->parent) {
if (of_device_is_compatible(node, "riscv")) {
- rc = riscv_of_processor_hartid(node, hartid);
- if (!rc)
- return 0;
+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+ if (*hartid == ~0UL) {
+ pr_warn("Found CPU without hart ID\n");
+ return -ENODEV;
+ }
+ return 0;
}
}
--
2.34.1
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WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Atish Patra <atishp@atishpatra.org>,
Andrew Jones <ajones@ventanamicro.com>,
Sunil V L <sunilvl@ventanamicro.com>,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>
Subject: [PATCH v9 01/15] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Thu, 28 Sep 2023 11:41:53 +0530 [thread overview]
Message-ID: <20230928061207.1841513-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230928061207.1841513-1-apatel@ventanamicro.com>
The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:
[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().
Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
*/
int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
{
- int rc;
-
for (; node; node = node->parent) {
if (of_device_is_compatible(node, "riscv")) {
- rc = riscv_of_processor_hartid(node, hartid);
- if (!rc)
- return 0;
+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+ if (*hartid == ~0UL) {
+ pr_warn("Found CPU without hart ID\n");
+ return -ENODEV;
+ }
+ return 0;
}
}
--
2.34.1
next prev parent reply other threads:[~2023-09-28 6:12 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-28 6:11 [PATCH v9 00/15] Linux RISC-V AIA Support Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 6:11 ` Anup Patel [this message]
2023-09-28 6:11 ` [PATCH v9 01/15] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-09-28 6:11 ` [PATCH v9 02/15] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 14:39 ` Rob Herring
2023-09-28 14:39 ` Rob Herring
2023-09-29 0:09 ` Saravana Kannan
2023-09-29 0:09 ` Saravana Kannan
2023-09-28 6:11 ` [PATCH v9 03/15] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 6:11 ` [PATCH v9 04/15] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 6:11 ` [PATCH v9 05/15] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-29 12:32 ` Marc Zyngier
2023-09-29 12:32 ` Marc Zyngier
2023-10-02 15:18 ` Anup Patel
2023-10-02 15:18 ` Anup Patel
2023-09-28 6:11 ` [PATCH v9 06/15] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 6:11 ` [PATCH v9 07/15] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-09-28 6:11 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 08/15] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 09/15] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 10/15] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 11/15] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 12/15] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 13/15] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 14/15] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-09-28 6:12 ` Anup Patel
2023-09-28 6:12 ` [PATCH v9 15/15] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-09-28 6:12 ` Anup Patel
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