From: Rob Herring <robh@kernel.org>
To: Nitin Rawat <quic_nitirawa@quicinc.com>
Cc: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, mani@kernel.org,
alim.akhtar@samsung.com, bvanassche@acm.org, avri.altman@wdc.com,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
cros-qcom-dts-watchers@chromium.org,
linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH V3 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS
Date: Thu, 28 Sep 2023 12:04:02 -0500 [thread overview]
Message-ID: <20230928170402.GA852313-robh@kernel.org> (raw)
In-Reply-To: <20230927082700.17593-1-quic_nitirawa@quicinc.com>
On Wed, Sep 27, 2023 at 01:57:00PM +0530, Nitin Rawat wrote:
> Align the binding property for clock such that "clocks" property
> comes first followed by "clock-names" property.
Why do we care?
>
> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
> ---
> .../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 802640efa956..d17bdc4e934f 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -295,14 +295,6 @@ examples:
> <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
> interconnect-names = "ufs-ddr", "cpu-ufs";
>
> - clock-names = "core_clk",
> - "bus_aggr_clk",
> - "iface_clk",
> - "core_clk_unipro",
> - "ref_clk",
> - "tx_lane0_sync_clk",
> - "rx_lane0_sync_clk",
> - "rx_lane1_sync_clk";
> clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> <&gcc GCC_UFS_PHY_AHB_CLK>,
> @@ -311,6 +303,14 @@ examples:
> <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> freq-table-hz = <75000000 300000000>,
> <0 0>,
> <0 0>,
> --
> 2.17.1
>
next prev parent reply other threads:[~2023-09-28 17:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-27 8:27 [PATCH V3 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS Nitin Rawat
2023-09-28 17:04 ` Rob Herring [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-09-27 8:18 [PATCH V3 0/4] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat
2023-09-27 8:18 ` [PATCH V3 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS Nitin Rawat
2023-09-27 8:29 ` Nitin Rawat
2023-09-27 9:27 ` Konrad Dybcio
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