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From: "David E. Box" <david.e.box@linux.intel.com>
To: linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org,
	ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: [PATCH V2 12/13] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P
Date: Tue,  3 Oct 2023 19:02:21 -0700	[thread overview]
Message-ID: <20231004020222.193445-13-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20231004020222.193445-1-david.e.box@linux.intel.com>

From: Xi Pardee <xi.pardee@intel.com>

Add support to read the low power mode requirements for Meteor Lake M and
Meteor Lake P.

Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
V2 - fixed unused return value

 drivers/platform/x86/intel/pmc/mtl.c | 41 +++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 7 deletions(-)

diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
index 780874142a90..78c9a80bd929 100644
--- a/drivers/platform/x86/intel/pmc/mtl.c
+++ b/drivers/platform/x86/intel/pmc/mtl.c
@@ -11,6 +11,13 @@
 #include <linux/pci.h>
 #include "core.h"
 
+/* PMC SSRAM PMT Telemetry GUIDS */
+#define SOCP_LPM_REQ_GUID	0x2625030
+#define IOEM_LPM_REQ_GUID	0x4357464
+#define IOEP_LPM_REQ_GUID	0x5077612
+
+static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20};
+
 /*
  * Die Mapping to Product.
  * Product SOCDie IOEDie PCHDie
@@ -465,6 +472,7 @@ const struct pmc_reg_map mtl_socm_reg_map = {
 	.lpm_sts = mtl_socm_lpm_maps,
 	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
 	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
+	.lpm_reg_index = MTL_LPM_REG_INDEX,
 };
 
 const struct pmc_bit_map mtl_ioep_pfear_map[] = {
@@ -782,6 +790,13 @@ const struct pmc_reg_map mtl_ioep_reg_map = {
 	.ltr_show_sts = mtl_ioep_ltr_show_map,
 	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 	.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
+	.lpm_num_maps = ADL_LPM_NUM_MAPS,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
+	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
+	.lpm_en_offset = MTL_LPM_EN_OFFSET,
+	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_reg_index = MTL_LPM_REG_INDEX,
 };
 
 const struct pmc_bit_map mtl_ioem_pfear_map[] = {
@@ -922,6 +937,13 @@ const struct pmc_reg_map mtl_ioem_reg_map = {
 	.ltr_show_sts = mtl_ioep_ltr_show_map,
 	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
 	.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
+	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_num_maps = ADL_LPM_NUM_MAPS,
+	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
+	.lpm_en_offset = MTL_LPM_EN_OFFSET,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
+	.lpm_reg_index = MTL_LPM_REG_INDEX,
 };
 
 #define PMC_DEVID_SOCM	0x7e7f
@@ -929,16 +951,19 @@ const struct pmc_reg_map mtl_ioem_reg_map = {
 #define PMC_DEVID_IOEM	0x7ebf
 static struct pmc_info mtl_pmc_info_list[] = {
 	{
-		.devid = PMC_DEVID_SOCM,
-		.map = &mtl_socm_reg_map,
+		.guid	= SOCP_LPM_REQ_GUID,
+		.devid	= PMC_DEVID_SOCM,
+		.map	= &mtl_socm_reg_map,
 	},
 	{
-		.devid = PMC_DEVID_IOEP,
-		.map = &mtl_ioep_reg_map,
+		.guid	= IOEP_LPM_REQ_GUID,
+		.devid	= PMC_DEVID_IOEP,
+		.map	= &mtl_ioep_reg_map,
 	},
 	{
-		.devid = PMC_DEVID_IOEM,
-		.map = &mtl_ioem_reg_map
+		.guid	= IOEM_LPM_REQ_GUID,
+		.devid	= PMC_DEVID_IOEM,
+		.map	= &mtl_ioem_reg_map
 	},
 	{}
 };
@@ -1012,5 +1037,7 @@ int mtl_core_init(struct pmc_dev *pmcdev)
 	dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
 	pmc_core_send_ltr_ignore(pmcdev, 3);
 
-	return 0;
+	ret = pmc_core_ssram_get_lpm_reqs(pmcdev);
+
+	return ret;
 }
-- 
2.34.1


  parent reply	other threads:[~2023-10-04  2:04 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-04  2:02 [PATCH V2 00/13] intel_pmc: Add telemetry API to read counters David E. Box
2023-10-04  2:02 ` [PATCH V2 01/13] platform/x86/intel/vsec: Move structures to header David E. Box
2023-10-04  7:24   ` Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 02/13] platform/x86/intel/vsec: remove platform_info from vsec device structure David E. Box
2023-10-04  7:27   ` Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 03/13] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-10-04  7:44   ` Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 04/13] platform/x86/intel/vsec: Add base address field David E. Box
2023-10-04  2:02 ` [PATCH V2 05/13] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-10-04  2:02 ` [PATCH V2 06/13] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-10-04  7:22   ` Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 07/13] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init David E. Box
2023-10-04  7:45   ` Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 08/13] platform/x86/intel/pmc: Split pmc_core_ssram_get_pmc() David E. Box
2023-10-04  2:02 ` [PATCH V2 09/13] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-10-04  2:02 ` [PATCH V2 10/13] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-10-04  2:02 ` [PATCH V2 11/13] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-10-04  2:02 ` David E. Box [this message]
2023-10-04  7:48   ` [PATCH V2 12/13] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P Ilpo Järvinen
2023-10-04  2:02 ` [PATCH V2 13/13] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box

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