From mboxrd@z Thu Jan 1 00:00:00 1970 From: Clément Léger Date: Wed, 4 Oct 2023 16:30:50 +0200 Subject: [PATCH 1/5] riscv: use ".L" local labels in assembly when applicable In-Reply-To: <20231004143054.482091-1-cleger@rivosinc.com> References: <20231004143054.482091-1-cleger@rivosinc.com> Message-ID: <20231004143054.482091-2-cleger@rivosinc.com> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit For the sake of coherency, use local labels in assembly when applicable. This also avoid kprobes being confused when applying a kprobe since the size of function is computed by checking where the next visible symbol is located. This might end up in computing some function size to be way shorter than expected and thus failing to apply kprobes to the specified offset. Signed-off-by: Cl?ment L?ger --- arch/riscv/kernel/entry.S | 10 +++---- arch/riscv/kernel/head.S | 18 ++++++------- arch/riscv/kernel/mcount.S | 10 +++---- arch/riscv/lib/memmove.S | 54 +++++++++++++++++++------------------- 4 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 143a2bb3e697..64ac0dd6176b 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -21,9 +21,9 @@ SYM_CODE_START(handle_exception) * register will contain 0, and we should continue on the current TP. */ csrrw tp, CSR_SCRATCH, tp - bnez tp, _save_context + bnez tp, .Lsave_context -_restore_kernel_tpsp: +.Lrestore_kernel_tpsp: csrr tp, CSR_SCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) @@ -35,7 +35,7 @@ _restore_kernel_tpsp: REG_L sp, TASK_TI_KERNEL_SP(tp) #endif -_save_context: +.Lsave_context: REG_S sp, TASK_TI_USER_SP(tp) REG_L sp, TASK_TI_KERNEL_SP(tp) addi sp, sp, -(PT_SIZE_ON_STACK) @@ -205,10 +205,10 @@ SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) REG_S x30, PT_T5(sp) REG_S x31, PT_T6(sp) - la ra, restore_caller_reg + la ra, .Lrestore_caller_reg tail get_overflow_stack -restore_caller_reg: +.Lrestore_caller_reg: //save per-cpu overflow stack REG_S a0, -8(sp) //restore caller register from shadow_stack diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3710ea5d160f..7e1b83f18a50 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -168,12 +168,12 @@ secondary_start_sbi: XIP_FIXUP_OFFSET a0 call relocate_enable_mmu #endif - call setup_trap_vector + call .Lsetup_trap_vector tail smp_callin #endif /* CONFIG_SMP */ .align 2 -setup_trap_vector: +.Lsetup_trap_vector: /* Set trap vector to exception handler */ la a0, handle_exception csrw CSR_TVEC, a0 @@ -210,7 +210,7 @@ ENTRY(_start_kernel) * not implement PMPs, so we set up a quick trap handler to just skip * touching the PMPs on any trap. */ - la a0, pmp_done + la a0, .Lpmp_done csrw CSR_TVEC, a0 li a0, -1 @@ -218,7 +218,7 @@ ENTRY(_start_kernel) li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X) csrw CSR_PMPCFG0, a0 .align 2 -pmp_done: +.Lpmp_done: /* * The hartid in a0 is expected later on, and we have no firmware @@ -282,12 +282,12 @@ pmp_done: /* Clear BSS for flat non-ELF images */ la a3, __bss_start la a4, __bss_stop - ble a4, a3, clear_bss_done -clear_bss: + ble a4, a3, .Lclear_bss_done +.Lclear_bss: REG_S zero, (a3) add a3, a3, RISCV_SZPTR - blt a3, a4, clear_bss -clear_bss_done: + blt a3, a4, .Lclear_bss +.Lclear_bss_done: #endif la a2, boot_cpu_hartid XIP_FIXUP_OFFSET a2 @@ -311,7 +311,7 @@ clear_bss_done: call relocate_enable_mmu #endif /* CONFIG_MMU */ - call setup_trap_vector + call .Lsetup_trap_vector /* Restore C environment */ la tp, init_task la sp, init_thread_union + THREAD_SIZE diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S index 8818a8fa9ff3..ab4dd0594fe7 100644 --- a/arch/riscv/kernel/mcount.S +++ b/arch/riscv/kernel/mcount.S @@ -85,16 +85,16 @@ ENTRY(MCOUNT_NAME) #ifdef CONFIG_FUNCTION_GRAPH_TRACER la t0, ftrace_graph_return REG_L t1, 0(t0) - bne t1, t4, do_ftrace_graph_caller + bne t1, t4, .Ldo_ftrace_graph_caller la t3, ftrace_graph_entry REG_L t2, 0(t3) la t6, ftrace_graph_entry_stub - bne t2, t6, do_ftrace_graph_caller + bne t2, t6, .Ldo_ftrace_graph_caller #endif la t3, ftrace_trace_function REG_L t5, 0(t3) - bne t5, t4, do_trace + bne t5, t4, .Ldo_trace ret #ifdef CONFIG_FUNCTION_GRAPH_TRACER @@ -102,7 +102,7 @@ ENTRY(MCOUNT_NAME) * A pseudo representation for the function graph tracer: * prepare_to_return(&ra_to_caller_of_caller, ra_to_caller) */ -do_ftrace_graph_caller: +.Ldo_ftrace_graph_caller: addi a0, s0, -SZREG mv a1, ra #ifdef HAVE_FUNCTION_GRAPH_FP_TEST @@ -118,7 +118,7 @@ do_ftrace_graph_caller: * A pseudo representation for the function tracer: * (*ftrace_trace_function)(ra_to_caller, ra_to_caller_of_caller) */ -do_trace: +.Ldo_trace: REG_L a1, -SZREG(s0) mv a0, ra diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index 838ff2022fe3..1930b388c3a0 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -26,8 +26,8 @@ SYM_FUNC_START_WEAK(memmove) */ /* Return if nothing to do */ - beq a0, a1, return_from_memmove - beqz a2, return_from_memmove + beq a0, a1, .Lreturn_from_memmove + beqz a2, .Lreturn_from_memmove /* * Register Uses @@ -60,7 +60,7 @@ SYM_FUNC_START_WEAK(memmove) * small enough not to bother. */ andi t0, a2, -(2 * SZREG) - beqz t0, byte_copy + beqz t0, .Lbyte_copy /* * Now solve for t5 and t6. @@ -87,14 +87,14 @@ SYM_FUNC_START_WEAK(memmove) */ xor t0, a0, a1 andi t1, t0, (SZREG - 1) - beqz t1, coaligned_copy + beqz t1, .Lcoaligned_copy /* Fall through to misaligned fixup copy */ -misaligned_fixup_copy: - bltu a1, a0, misaligned_fixup_copy_reverse +.Lmisaligned_fixup_copy: + bltu a1, a0, .Lmisaligned_fixup_copy_reverse -misaligned_fixup_copy_forward: - jal t0, byte_copy_until_aligned_forward +.Lmisaligned_fixup_copy_forward: + jal t0, .Lbyte_copy_until_aligned_forward andi a5, a1, (SZREG - 1) /* Find the alignment offset of src (a1) */ slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ @@ -153,10 +153,10 @@ misaligned_fixup_copy_forward: mv t3, t6 /* Fix the dest pointer in case the loop was broken */ add a1, t3, a5 /* Restore the src pointer */ - j byte_copy_forward /* Copy any remaining bytes */ + j .Lbyte_copy_forward /* Copy any remaining bytes */ -misaligned_fixup_copy_reverse: - jal t0, byte_copy_until_aligned_reverse +.Lmisaligned_fixup_copy_reverse: + jal t0, .Lbyte_copy_until_aligned_reverse andi a5, a4, (SZREG - 1) /* Find the alignment offset of src (a4) */ slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ @@ -215,18 +215,18 @@ misaligned_fixup_copy_reverse: mv t4, t5 /* Fix the dest pointer in case the loop was broken */ add a4, t4, a5 /* Restore the src pointer */ - j byte_copy_reverse /* Copy any remaining bytes */ + j .Lbyte_copy_reverse /* Copy any remaining bytes */ /* * Simple copy loops for SZREG co-aligned memory locations. * These also make calls to do byte copies for any unaligned * data at their terminations. */ -coaligned_copy: - bltu a1, a0, coaligned_copy_reverse +.Lcoaligned_copy: + bltu a1, a0, .Lcoaligned_copy_reverse -coaligned_copy_forward: - jal t0, byte_copy_until_aligned_forward +.Lcoaligned_copy_forward: + jal t0, .Lbyte_copy_until_aligned_forward 1: REG_L t1, ( 0 * SZREG)(a1) @@ -235,10 +235,10 @@ coaligned_copy_forward: REG_S t1, (-1 * SZREG)(t3) bne t3, t6, 1b - j byte_copy_forward /* Copy any remaining bytes */ + j .Lbyte_copy_forward /* Copy any remaining bytes */ -coaligned_copy_reverse: - jal t0, byte_copy_until_aligned_reverse +.Lcoaligned_copy_reverse: + jal t0, .Lbyte_copy_until_aligned_reverse 1: REG_L t1, (-1 * SZREG)(a4) @@ -247,7 +247,7 @@ coaligned_copy_reverse: REG_S t1, ( 0 * SZREG)(t4) bne t4, t5, 1b - j byte_copy_reverse /* Copy any remaining bytes */ + j .Lbyte_copy_reverse /* Copy any remaining bytes */ /* * These are basically sub-functions within the function. They @@ -258,7 +258,7 @@ coaligned_copy_reverse: * up from where they were left and we avoid code duplication * without any overhead except the call in and return jumps. */ -byte_copy_until_aligned_forward: +.Lbyte_copy_until_aligned_forward: beq t3, t5, 2f 1: lb t1, 0(a1) @@ -269,7 +269,7 @@ byte_copy_until_aligned_forward: 2: jalr zero, 0x0(t0) /* Return to multibyte copy loop */ -byte_copy_until_aligned_reverse: +.Lbyte_copy_until_aligned_reverse: beq t4, t6, 2f 1: lb t1, -1(a4) @@ -285,10 +285,10 @@ byte_copy_until_aligned_reverse: * These will byte copy until they reach the end of data to copy. * At that point, they will call to return from memmove. */ -byte_copy: - bltu a1, a0, byte_copy_reverse +.Lbyte_copy: + bltu a1, a0, .Lbyte_copy_reverse -byte_copy_forward: +.Lbyte_copy_forward: beq t3, t4, 2f 1: lb t1, 0(a1) @@ -299,7 +299,7 @@ byte_copy_forward: 2: ret -byte_copy_reverse: +.Lbyte_copy_reverse: beq t4, t3, 2f 1: lb t1, -1(a4) @@ -309,7 +309,7 @@ byte_copy_reverse: bne t4, t3, 1b 2: -return_from_memmove: +.Lreturn_from_memmove: ret SYM_FUNC_END(memmove) -- 2.42.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 976DBE7C4CA for ; Wed, 4 Oct 2023 14:35:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oWpOI6uJLTKBLr/dOybfVV6Tg4HlfiE/qqLN1oL1W2c=; b=nCmDao2GteBfOn yXw5rxahaWc2LgyFQ4rn8MO8niLA0ldbxQtrLnBtTxzvVisqfg4nRFSn8rm8rPl4y5l0f3Luj15nN vinxzYx01OssZrQoPVo92eXQEXyzfmO2O3nHRhmj9ON8R9U4yyFvWCn8EcYcxGDTnL73gUTMlgcnP QOgxEgCKx6N/DqPrNZSSyrTJ7FU9YLRWOnDQo6rWcT+9NMyXMU252r3jCCWO+DbYOF7GvAzk4y7DX R3NxnZjpuy5Shm1fdnFY/sBUmKTc3EAl7UXHHeDjJ0XOm3FuhrhOJuJb7wXB0DuGRucvv6lZ9EDG0 MVw8ItwVXxcA1oJYA7Pw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qo2xh-000ENg-1I; Wed, 04 Oct 2023 14:34:53 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qo2xb-000EJF-26 for linux-riscv@lists.infradead.org; Wed, 04 Oct 2023 14:34:51 +0000 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-405d70d19bcso3906635e9.0 for ; Wed, 04 Oct 2023 07:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696430085; x=1697034885; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r99tKuV5xWrXesJjmtv6oJbCMc9/ubfSXf75DUqKcqw=; b=wdgtQZphSRoSOKI38IoEC3Y2E0J+EPYCbtkN3ecPQkiz2cYtQVHGrO9Lk6J+LkG8/B KJW8vXZulTNaZ1S82m9qjioaXz1OsC5SHxjnpHQUefI4beJB74wqR/WghH5gLkm3qeM4 m0nGnfsq9T/uvMGBt/qlbbKEf99loEzEdCJdP2Zs8n0phghS6/vZhrOGxiccEt+0QIcQ 9Valt+hrVJlyTqkDZ7yADguiJQZyGf4y1BfY0KSVKSHtN7xoKFILXUSmldycMKPzjZey Wd5jTkHXi9Px1Z3Q+fGKpzSBFsAS8NglmuHJxUoXj2sKfAk7ae4szKyOA+2hIQ+4HhQZ k1UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696430085; x=1697034885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r99tKuV5xWrXesJjmtv6oJbCMc9/ubfSXf75DUqKcqw=; b=tMK9VZ8MSh2bDZe3yFkoTuU8MeAkEXUBR/nn0ADej7Oko4cTlrYQ3TA4skQM7XdeiW 4bb2iWFxWdg85HKiOj3kcN4eycU6Kl1GxFdQN0wZnTLOxG71B0nHZzG6RWdLrdxP1TnF 8R3urgqfTqIBXL2T6wYO/3CQBW2eM+f/t1TLXFciv2FXcMvhfGa3VhHqn2/BbyoH2Etn 349w5ZpZyEQGCYAMdyJH8Hi2NW8e4IXjSpZtuc0bPb6pLpmkAoIT0v5PED+NIzL45jgq B3HfLT/ulUtRyKDYj9a0QmaMlTPJ5Kdjh2HRSCYPpYCIXiQMPXX4LdORkXsiRpF/Or0X Dm4g== X-Gm-Message-State: AOJu0YwyAko/dvhiyjusUplVmQbiKTkhwtkMqeHI/0p1KvGEQAdYFi2p fdTzr1Iz8SjoaCBRJVgjBmavvg== X-Google-Smtp-Source: AGHT+IEhTtkHofspQsCrchLDsOfNanY9EaHniKPm9Ne23xsRejQeETojJh33Njn26JvODcLm0P0sNg== X-Received: by 2002:a05:600c:1d03:b0:405:39bb:38a8 with SMTP id l3-20020a05600c1d0300b0040539bb38a8mr2410140wms.2.1696430084758; Wed, 04 Oct 2023 07:34:44 -0700 (PDT) Received: from carbon-x1.. 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IDEwICsrKy0tLS0KIGFyY2gvcmlzY3Yva2VybmVsL2hlYWQuUyAgIHwgMTggKysrKysrLS0tLS0t LQogYXJjaC9yaXNjdi9rZXJuZWwvbWNvdW50LlMgfCAxMCArKystLS0tCiBhcmNoL3Jpc2N2L2xp Yi9tZW1tb3ZlLlMgICB8IDU0ICsrKysrKysrKysrKysrKysrKystLS0tLS0tLS0tLS0tLS0tLS0t CiA0IGZpbGVzIGNoYW5nZWQsIDQ2IGluc2VydGlvbnMoKyksIDQ2IGRlbGV0aW9ucygtKQoKZGlm ZiAtLWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMgYi9hcmNoL3Jpc2N2L2tlcm5lbC9l bnRyeS5TCmluZGV4IDE0M2EyYmIzZTY5Ny4uNjRhYzBkZDYxNzZiIDEwMDY0NAotLS0gYS9hcmNo L3Jpc2N2L2tlcm5lbC9lbnRyeS5TCisrKyBiL2FyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMKQEAg LTIxLDkgKzIxLDkgQEAgU1lNX0NPREVfU1RBUlQoaGFuZGxlX2V4Y2VwdGlvbikKIAkgKiByZWdp c3RlciB3aWxsIGNvbnRhaW4gMCwgYW5kIHdlIHNob3VsZCBjb250aW51ZSBvbiB0aGUgY3VycmVu dCBUUC4KIAkgKi8KIAljc3JydyB0cCwgQ1NSX1NDUkFUQ0gsIHRwCi0JYm5leiB0cCwgX3NhdmVf Y29udGV4dAorCWJuZXogdHAsIC5Mc2F2ZV9jb250ZXh0CiAKLV9yZXN0b3JlX2tlcm5lbF90cHNw OgorLkxyZXN0b3JlX2tlcm5lbF90cHNwOgogCWNzcnIgdHAsIENTUl9TQ1JBVENICiAJUkVHX1Mg c3AsIFRBU0tfVElfS0VSTkVMX1NQKHRwKQogCkBAIC0zNSw3ICszNSw3IEBAIF9yZXN0b3JlX2tl cm5lbF90cHNwOgogCVJFR19MIHNwLCBUQVNLX1RJX0tFUk5FTF9TUCh0cCkKICNlbmRpZgogCi1f c2F2ZV9jb250ZXh0OgorLkxzYXZlX2NvbnRleHQ6CiAJUkVHX1Mgc3AsIFRBU0tfVElfVVNFUl9T UCh0cCkKIAlSRUdfTCBzcCwgVEFTS19USV9LRVJORUxfU1AodHApCiAJYWRkaSBzcCwgc3AsIC0o UFRfU0laRV9PTl9TVEFDSykKQEAgLTIwNSwxMCArMjA1LDEwIEBAIFNZTV9DT0RFX1NUQVJUX0xP Q0FMKGhhbmRsZV9rZXJuZWxfc3RhY2tfb3ZlcmZsb3cpCiAJUkVHX1MgeDMwLCBQVF9UNShzcCkK IAlSRUdfUyB4MzEsIFBUX1Q2KHNwKQogCi0JbGEgcmEsIHJlc3RvcmVfY2FsbGVyX3JlZworCWxh IHJhLCAuTHJlc3RvcmVfY2FsbGVyX3JlZwogCXRhaWwgZ2V0X292ZXJmbG93X3N0YWNrCiAKLXJl c3RvcmVfY2FsbGVyX3JlZzoKKy5McmVzdG9yZV9jYWxsZXJfcmVnOgogCS8vc2F2ZSBwZXItY3B1 IG92ZXJmbG93IHN0YWNrCiAJUkVHX1MgYTAsIC04KHNwKQogCS8vcmVzdG9yZSBjYWxsZXIgcmVn aXN0ZXIgZnJvbSBzaGFkb3dfc3RhY2sKZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2hl YWQuUyBiL2FyY2gvcmlzY3Yva2VybmVsL2hlYWQuUwppbmRleCAzNzEwZWE1ZDE2MGYuLjdlMWI4 M2YxOGE1MCAxMDA2NDQKLS0tIGEvYXJjaC9yaXNjdi9rZXJuZWwvaGVhZC5TCisrKyBiL2FyY2gv cmlzY3Yva2VybmVsL2hlYWQuUwpAQCAtMTY4LDEyICsxNjgsMTIgQEAgc2Vjb25kYXJ5X3N0YXJ0 X3NiaToKIAlYSVBfRklYVVBfT0ZGU0VUIGEwCiAJY2FsbCByZWxvY2F0ZV9lbmFibGVfbW11CiAj ZW5kaWYKLQljYWxsIHNldHVwX3RyYXBfdmVjdG9yCisJY2FsbCAuTHNldHVwX3RyYXBfdmVjdG9y CiAJdGFpbCBzbXBfY2FsbGluCiAjZW5kaWYgLyogQ09ORklHX1NNUCAqLwogCiAuYWxpZ24gMgot c2V0dXBfdHJhcF92ZWN0b3I6CisuTHNldHVwX3RyYXBfdmVjdG9yOgogCS8qIFNldCB0cmFwIHZl Y3RvciB0byBleGNlcHRpb24gaGFuZGxlciAqLwogCWxhIGEwLCBoYW5kbGVfZXhjZXB0aW9uCiAJ Y3NydyBDU1JfVFZFQywgYTAKQEAgLTIxMCw3ICsyMTAsNyBAQCBFTlRSWShfc3RhcnRfa2VybmVs KQogCSAqIG5vdCBpbXBsZW1lbnQgUE1Qcywgc28gd2Ugc2V0IHVwIGEgcXVpY2sgdHJhcCBoYW5k bGVyIHRvIGp1c3Qgc2tpcAogCSAqIHRvdWNoaW5nIHRoZSBQTVBzIG9uIGFueSB0cmFwLgogCSAq LwotCWxhIGEwLCBwbXBfZG9uZQorCWxhIGEwLCAuTHBtcF9kb25lCiAJY3NydyBDU1JfVFZFQywg YTAKIAogCWxpIGEwLCAtMQpAQCAtMjE4LDcgKzIxOCw3IEBAIEVOVFJZKF9zdGFydF9rZXJuZWwp CiAJbGkgYTAsIChQTVBfQV9OQVBPVCB8IFBNUF9SIHwgUE1QX1cgfCBQTVBfWCkKIAljc3J3IENT Ul9QTVBDRkcwLCBhMAogLmFsaWduIDIKLXBtcF9kb25lOgorLkxwbXBfZG9uZToKIAogCS8qCiAJ ICogVGhlIGhhcnRpZCBpbiBhMCBpcyBleHBlY3RlZCBsYXRlciBvbiwgYW5kIHdlIGhhdmUgbm8g ZmlybXdhcmUKQEAgLTI4MiwxMiArMjgyLDEyIEBAIHBtcF9kb25lOgogCS8qIENsZWFyIEJTUyBm b3IgZmxhdCBub24tRUxGIGltYWdlcyAqLwogCWxhIGEzLCBfX2Jzc19zdGFydAogCWxhIGE0LCBf X2Jzc19zdG9wCi0JYmxlIGE0LCBhMywgY2xlYXJfYnNzX2RvbmUKLWNsZWFyX2JzczoKKwlibGUg YTQsIGEzLCAuTGNsZWFyX2Jzc19kb25lCisuTGNsZWFyX2JzczoKIAlSRUdfUyB6ZXJvLCAoYTMp CiAJYWRkIGEzLCBhMywgUklTQ1ZfU1pQVFIKLQlibHQgYTMsIGE0LCBjbGVhcl9ic3MKLWNsZWFy X2Jzc19kb25lOgorCWJsdCBhMywgYTQsIC5MY2xlYXJfYnNzCisuTGNsZWFyX2Jzc19kb25lOgog I2VuZGlmCiAJbGEgYTIsIGJvb3RfY3B1X2hhcnRpZAogCVhJUF9GSVhVUF9PRkZTRVQgYTIKQEAg LTMxMSw3ICszMTEsNyBAQCBjbGVhcl9ic3NfZG9uZToKIAljYWxsIHJlbG9jYXRlX2VuYWJsZV9t bXUKICNlbmRpZiAvKiBDT05GSUdfTU1VICovCiAKLQljYWxsIHNldHVwX3RyYXBfdmVjdG9yCisJ Y2FsbCAuTHNldHVwX3RyYXBfdmVjdG9yCiAJLyogUmVzdG9yZSBDIGVudmlyb25tZW50ICovCiAJ bGEgdHAsIGluaXRfdGFzawogCWxhIHNwLCBpbml0X3RocmVhZF91bmlvbiArIFRIUkVBRF9TSVpF CmRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L2tlcm5lbC9tY291bnQuUyBiL2FyY2gvcmlzY3Yva2Vy bmVsL21jb3VudC5TCmluZGV4IDg4MThhOGZhOWZmMy4uYWI0ZGQwNTk0ZmU3IDEwMDY0NAotLS0g YS9hcmNoL3Jpc2N2L2tlcm5lbC9tY291bnQuUworKysgYi9hcmNoL3Jpc2N2L2tlcm5lbC9tY291 bnQuUwpAQCAtODUsMTYgKzg1LDE2IEBAIEVOVFJZKE1DT1VOVF9OQU1FKQogI2lmZGVmIENPTkZJ R19GVU5DVElPTl9HUkFQSF9UUkFDRVIKIAlsYQl0MCwgZnRyYWNlX2dyYXBoX3JldHVybgogCVJF R19MCXQxLCAwKHQwKQotCWJuZQl0MSwgdDQsIGRvX2Z0cmFjZV9ncmFwaF9jYWxsZXIKKwlibmUJ dDEsIHQ0LCAuTGRvX2Z0cmFjZV9ncmFwaF9jYWxsZXIKIAogCWxhCXQzLCBmdHJhY2VfZ3JhcGhf ZW50cnkKIAlSRUdfTAl0MiwgMCh0MykKIAlsYQl0NiwgZnRyYWNlX2dyYXBoX2VudHJ5X3N0dWIK LQlibmUJdDIsIHQ2LCBkb19mdHJhY2VfZ3JhcGhfY2FsbGVyCisJYm5lCXQyLCB0NiwgLkxkb19m dHJhY2VfZ3JhcGhfY2FsbGVyCiAjZW5kaWYKIAlsYQl0MywgZnRyYWNlX3RyYWNlX2Z1bmN0aW9u CiAJUkVHX0wJdDUsIDAodDMpCi0JYm5lCXQ1LCB0NCwgZG9fdHJhY2UKKwlibmUJdDUsIHQ0LCAu TGRvX3RyYWNlCiAJcmV0CiAKICNpZmRlZiBDT05GSUdfRlVOQ1RJT05fR1JBUEhfVFJBQ0VSCkBA IC0xMDIsNyArMTAyLDcgQEAgRU5UUlkoTUNPVU5UX05BTUUpCiAgKiBBIHBzZXVkbyByZXByZXNl bnRhdGlvbiBmb3IgdGhlIGZ1bmN0aW9uIGdyYXBoIHRyYWNlcjoKICAqIHByZXBhcmVfdG9fcmV0 dXJuKCZyYV90b19jYWxsZXJfb2ZfY2FsbGVyLCByYV90b19jYWxsZXIpCiAgKi8KLWRvX2Z0cmFj ZV9ncmFwaF9jYWxsZXI6CisuTGRvX2Z0cmFjZV9ncmFwaF9jYWxsZXI6CiAJYWRkaQlhMCwgczAs IC1TWlJFRwogCW12CWExLCByYQogI2lmZGVmIEhBVkVfRlVOQ1RJT05fR1JBUEhfRlBfVEVTVApA QCAtMTE4LDcgKzExOCw3IEBAIGRvX2Z0cmFjZV9ncmFwaF9jYWxsZXI6CiAgKiBBIHBzZXVkbyBy ZXByZXNlbnRhdGlvbiBmb3IgdGhlIGZ1bmN0aW9uIHRyYWNlcjoKICAqICgqZnRyYWNlX3RyYWNl X2Z1bmN0aW9uKShyYV90b19jYWxsZXIsIHJhX3RvX2NhbGxlcl9vZl9jYWxsZXIpCiAgKi8KLWRv X3RyYWNlOgorLkxkb190cmFjZToKIAlSRUdfTAlhMSwgLVNaUkVHKHMwKQogCW12CWEwLCByYQog CmRpZmYgLS1naXQgYS9hcmNoL3Jpc2N2L2xpYi9tZW1tb3ZlLlMgYi9hcmNoL3Jpc2N2L2xpYi9t ZW1tb3ZlLlMKaW5kZXggODM4ZmYyMDIyZmUzLi4xOTMwYjM4OGMzYTAgMTAwNjQ0Ci0tLSBhL2Fy Y2gvcmlzY3YvbGliL21lbW1vdmUuUworKysgYi9hcmNoL3Jpc2N2L2xpYi9tZW1tb3ZlLlMKQEAg LTI2LDggKzI2LDggQEAgU1lNX0ZVTkNfU1RBUlRfV0VBSyhtZW1tb3ZlKQogCSAqLwogCiAJLyog UmV0dXJuIGlmIG5vdGhpbmcgdG8gZG8gKi8KLQliZXEgYTAsIGExLCByZXR1cm5fZnJvbV9tZW1t b3ZlCi0JYmVxeiBhMiwgcmV0dXJuX2Zyb21fbWVtbW92ZQorCWJlcSBhMCwgYTEsIC5McmV0dXJu X2Zyb21fbWVtbW92ZQorCWJlcXogYTIsIC5McmV0dXJuX2Zyb21fbWVtbW92ZQogCiAJLyoKIAkg KiBSZWdpc3RlciBVc2VzCkBAIC02MCw3ICs2MCw3IEBAIFNZTV9GVU5DX1NUQVJUX1dFQUsobWVt bW92ZSkKIAkgKiBzbWFsbCBlbm91Z2ggbm90IHRvIGJvdGhlci4KIAkgKi8KIAlhbmRpIHQwLCBh MiwgLSgyICogU1pSRUcpCi0JYmVxeiB0MCwgYnl0ZV9jb3B5CisJYmVxeiB0MCwgLkxieXRlX2Nv cHkKIAogCS8qCiAJICogTm93IHNvbHZlIGZvciB0NSBhbmQgdDYuCkBAIC04NywxNCArODcsMTQg QEAgU1lNX0ZVTkNfU1RBUlRfV0VBSyhtZW1tb3ZlKQogCSAqLwogCXhvciAgdDAsIGEwLCBhMQog CWFuZGkgdDEsIHQwLCAoU1pSRUcgLSAxKQotCWJlcXogdDEsIGNvYWxpZ25lZF9jb3B5CisJYmVx eiB0MSwgLkxjb2FsaWduZWRfY29weQogCS8qIEZhbGwgdGhyb3VnaCB0byBtaXNhbGlnbmVkIGZp eHVwIGNvcHkgKi8KIAotbWlzYWxpZ25lZF9maXh1cF9jb3B5OgotCWJsdHUgYTEsIGEwLCBtaXNh bGlnbmVkX2ZpeHVwX2NvcHlfcmV2ZXJzZQorLkxtaXNhbGlnbmVkX2ZpeHVwX2NvcHk6CisJYmx0 dSBhMSwgYTAsIC5MbWlzYWxpZ25lZF9maXh1cF9jb3B5X3JldmVyc2UKIAotbWlzYWxpZ25lZF9m aXh1cF9jb3B5X2ZvcndhcmQ6Ci0JamFsICB0MCwgYnl0ZV9jb3B5X3VudGlsX2FsaWduZWRfZm9y d2FyZAorLkxtaXNhbGlnbmVkX2ZpeHVwX2NvcHlfZm9yd2FyZDoKKwlqYWwgIHQwLCAuTGJ5dGVf Y29weV91bnRpbF9hbGlnbmVkX2ZvcndhcmQKIAogCWFuZGkgYTUsIGExLCAoU1pSRUcgLSAxKSAv KiBGaW5kIHRoZSBhbGlnbm1lbnQgb2Zmc2V0IG9mIHNyYyAoYTEpICovCiAJc2xsaSBhNiwgYTUs IDMgLyogTXVsdGlwbHkgYnkgOCB0byBjb252ZXJ0IHRoYXQgdG8gYml0cyB0byBzaGlmdCAqLwpA QCAtMTUzLDEwICsxNTMsMTAgQEAgbWlzYWxpZ25lZF9maXh1cF9jb3B5X2ZvcndhcmQ6CiAJbXYg ICAgdDMsIHQ2IC8qIEZpeCB0aGUgZGVzdCBwb2ludGVyIGluIGNhc2UgdGhlIGxvb3Agd2FzIGJy b2tlbiAqLwogCiAJYWRkICBhMSwgdDMsIGE1IC8qIFJlc3RvcmUgdGhlIHNyYyBwb2ludGVyICov Ci0JaiBieXRlX2NvcHlfZm9yd2FyZCAvKiBDb3B5IGFueSByZW1haW5pbmcgYnl0ZXMgKi8KKwlq IC5MYnl0ZV9jb3B5X2ZvcndhcmQgLyogQ29weSBhbnkgcmVtYWluaW5nIGJ5dGVzICovCiAKLW1p c2FsaWduZWRfZml4dXBfY29weV9yZXZlcnNlOgotCWphbCAgdDAsIGJ5dGVfY29weV91bnRpbF9h bGlnbmVkX3JldmVyc2UKKy5MbWlzYWxpZ25lZF9maXh1cF9jb3B5X3JldmVyc2U6CisJamFsICB0 MCwgLkxieXRlX2NvcHlfdW50aWxfYWxpZ25lZF9yZXZlcnNlCiAKIAlhbmRpIGE1LCBhNCwgKFNa UkVHIC0gMSkgLyogRmluZCB0aGUgYWxpZ25tZW50IG9mZnNldCBvZiBzcmMgKGE0KSAqLwogCXNs bGkgYTYsIGE1LCAzIC8qIE11bHRpcGx5IGJ5IDggdG8gY29udmVydCB0aGF0IHRvIGJpdHMgdG8g c2hpZnQgKi8KQEAgLTIxNSwxOCArMjE1LDE4IEBAIG1pc2FsaWduZWRfZml4dXBfY29weV9yZXZl cnNlOgogCW12ICAgIHQ0LCB0NSAvKiBGaXggdGhlIGRlc3QgcG9pbnRlciBpbiBjYXNlIHRoZSBs b29wIHdhcyBicm9rZW4gKi8KIAogCWFkZCAgYTQsIHQ0LCBhNSAvKiBSZXN0b3JlIHRoZSBzcmMg cG9pbnRlciAqLwotCWogYnl0ZV9jb3B5X3JldmVyc2UgLyogQ29weSBhbnkgcmVtYWluaW5nIGJ5 dGVzICovCisJaiAuTGJ5dGVfY29weV9yZXZlcnNlIC8qIENvcHkgYW55IHJlbWFpbmluZyBieXRl cyAqLwogCiAvKgogICogU2ltcGxlIGNvcHkgbG9vcHMgZm9yIFNaUkVHIGNvLWFsaWduZWQgbWVt b3J5IGxvY2F0aW9ucy4KICAqIFRoZXNlIGFsc28gbWFrZSBjYWxscyB0byBkbyBieXRlIGNvcGll cyBmb3IgYW55IHVuYWxpZ25lZAogICogZGF0YSBhdCB0aGVpciB0ZXJtaW5hdGlvbnMuCiAgKi8K LWNvYWxpZ25lZF9jb3B5OgotCWJsdHUgYTEsIGEwLCBjb2FsaWduZWRfY29weV9yZXZlcnNlCisu TGNvYWxpZ25lZF9jb3B5OgorCWJsdHUgYTEsIGEwLCAuTGNvYWxpZ25lZF9jb3B5X3JldmVyc2UK IAotY29hbGlnbmVkX2NvcHlfZm9yd2FyZDoKLQlqYWwgdDAsIGJ5dGVfY29weV91bnRpbF9hbGln bmVkX2ZvcndhcmQKKy5MY29hbGlnbmVkX2NvcHlfZm9yd2FyZDoKKwlqYWwgdDAsIC5MYnl0ZV9j b3B5X3VudGlsX2FsaWduZWRfZm9yd2FyZAogCiAJMToKIAlSRUdfTCB0MSwgKCAwICogU1pSRUcp KGExKQpAQCAtMjM1LDEwICsyMzUsMTAgQEAgY29hbGlnbmVkX2NvcHlfZm9yd2FyZDoKIAlSRUdf UyB0MSwgKC0xICogU1pSRUcpKHQzKQogCWJuZSAgIHQzLCB0NiwgMWIKIAotCWogYnl0ZV9jb3B5 X2ZvcndhcmQgLyogQ29weSBhbnkgcmVtYWluaW5nIGJ5dGVzICovCisJaiAuTGJ5dGVfY29weV9m b3J3YXJkIC8qIENvcHkgYW55IHJlbWFpbmluZyBieXRlcyAqLwogCi1jb2FsaWduZWRfY29weV9y ZXZlcnNlOgotCWphbCB0MCwgYnl0ZV9jb3B5X3VudGlsX2FsaWduZWRfcmV2ZXJzZQorLkxjb2Fs aWduZWRfY29weV9yZXZlcnNlOgorCWphbCB0MCwgLkxieXRlX2NvcHlfdW50aWxfYWxpZ25lZF9y ZXZlcnNlCiAKIAkxOgogCVJFR19MIHQxLCAoLTEgKiBTWlJFRykoYTQpCkBAIC0yNDcsNyArMjQ3 LDcgQEAgY29hbGlnbmVkX2NvcHlfcmV2ZXJzZToKIAlSRUdfUyB0MSwgKCAwICogU1pSRUcpKHQ0 KQogCWJuZSAgIHQ0LCB0NSwgMWIKIAotCWogYnl0ZV9jb3B5X3JldmVyc2UgLyogQ29weSBhbnkg cmVtYWluaW5nIGJ5dGVzICovCisJaiAuTGJ5dGVfY29weV9yZXZlcnNlIC8qIENvcHkgYW55IHJl bWFpbmluZyBieXRlcyAqLwogCiAvKgogICogVGhlc2UgYXJlIGJhc2ljYWxseSBzdWItZnVuY3Rp b25zIHdpdGhpbiB0aGUgZnVuY3Rpb24uICBUaGV5CkBAIC0yNTgsNyArMjU4LDcgQEAgY29hbGln bmVkX2NvcHlfcmV2ZXJzZToKICAqIHVwIGZyb20gd2hlcmUgdGhleSB3ZXJlIGxlZnQgYW5kIHdl IGF2b2lkIGNvZGUgZHVwbGljYXRpb24KICAqIHdpdGhvdXQgYW55IG92ZXJoZWFkIGV4Y2VwdCB0 aGUgY2FsbCBpbiBhbmQgcmV0dXJuIGp1bXBzLgogICovCi1ieXRlX2NvcHlfdW50aWxfYWxpZ25l ZF9mb3J3YXJkOgorLkxieXRlX2NvcHlfdW50aWxfYWxpZ25lZF9mb3J3YXJkOgogCWJlcSAgdDMs IHQ1LCAyZgogCTE6CiAJbGIgICB0MSwgIDAoYTEpCkBAIC0yNjksNyArMjY5LDcgQEAgYnl0ZV9j b3B5X3VudGlsX2FsaWduZWRfZm9yd2FyZDoKIAkyOgogCWphbHIgemVybywgMHgwKHQwKSAvKiBS ZXR1cm4gdG8gbXVsdGlieXRlIGNvcHkgbG9vcCAqLwogCi1ieXRlX2NvcHlfdW50aWxfYWxpZ25l ZF9yZXZlcnNlOgorLkxieXRlX2NvcHlfdW50aWxfYWxpZ25lZF9yZXZlcnNlOgogCWJlcSAgdDQs IHQ2LCAyZgogCTE6CiAJbGIgICB0MSwgLTEoYTQpCkBAIC0yODUsMTAgKzI4NSwxMCBAQCBieXRl X2NvcHlfdW50aWxfYWxpZ25lZF9yZXZlcnNlOgogICogVGhlc2Ugd2lsbCBieXRlIGNvcHkgdW50 aWwgdGhleSByZWFjaCB0aGUgZW5kIG9mIGRhdGEgdG8gY29weS4KICAqIEF0IHRoYXQgcG9pbnQs IHRoZXkgd2lsbCBjYWxsIHRvIHJldHVybiBmcm9tIG1lbW1vdmUuCiAgKi8KLWJ5dGVfY29weToK LQlibHR1IGExLCBhMCwgYnl0ZV9jb3B5X3JldmVyc2UKKy5MYnl0ZV9jb3B5OgorCWJsdHUgYTEs IGEwLCAuTGJ5dGVfY29weV9yZXZlcnNlCiAKLWJ5dGVfY29weV9mb3J3YXJkOgorLkxieXRlX2Nv cHlfZm9yd2FyZDoKIAliZXEgIHQzLCB0NCwgMmYKIAkxOgogCWxiICAgdDEsICAwKGExKQpAQCAt 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([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id t20-20020a1c7714000000b00401e32b25adsm1686205wmi.4.2023.10.04.07.34.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 07:34:44 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH 1/5] riscv: use ".L" local labels in assembly when applicable Date: Wed, 4 Oct 2023 16:30:50 +0200 Message-ID: <20231004143054.482091-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004143054.482091-1-cleger@rivosinc.com> References: <20231004143054.482091-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org For the sake of coherency, use local labels in assembly when applicable. This also avoid kprobes being confused when applying a kprobe since the size of function is computed by checking where the next visible symbol is located. This might end up in computing some function size to be way shorter than expected and thus failing to apply kprobes to the specified offset. Signed-off-by: Clément Léger --- arch/riscv/kernel/entry.S | 10 +++---- arch/riscv/kernel/head.S | 18 ++++++------- arch/riscv/kernel/mcount.S | 10 +++---- arch/riscv/lib/memmove.S | 54 +++++++++++++++++++------------------- 4 files changed, 46 insertions(+), 46 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 143a2bb3e697..64ac0dd6176b 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -21,9 +21,9 @@ SYM_CODE_START(handle_exception) * register will contain 0, and we should continue on the current TP. */ csrrw tp, CSR_SCRATCH, tp - bnez tp, _save_context + bnez tp, .Lsave_context -_restore_kernel_tpsp: +.Lrestore_kernel_tpsp: csrr tp, CSR_SCRATCH REG_S sp, TASK_TI_KERNEL_SP(tp) @@ -35,7 +35,7 @@ _restore_kernel_tpsp: REG_L sp, TASK_TI_KERNEL_SP(tp) #endif -_save_context: +.Lsave_context: REG_S sp, TASK_TI_USER_SP(tp) REG_L sp, TASK_TI_KERNEL_SP(tp) addi sp, sp, -(PT_SIZE_ON_STACK) @@ -205,10 +205,10 @@ SYM_CODE_START_LOCAL(handle_kernel_stack_overflow) REG_S x30, PT_T5(sp) REG_S x31, PT_T6(sp) - la ra, restore_caller_reg + la ra, .Lrestore_caller_reg tail get_overflow_stack -restore_caller_reg: +.Lrestore_caller_reg: //save per-cpu overflow stack REG_S a0, -8(sp) //restore caller register from shadow_stack diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3710ea5d160f..7e1b83f18a50 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -168,12 +168,12 @@ secondary_start_sbi: XIP_FIXUP_OFFSET a0 call relocate_enable_mmu #endif - call setup_trap_vector + call .Lsetup_trap_vector tail smp_callin #endif /* CONFIG_SMP */ .align 2 -setup_trap_vector: +.Lsetup_trap_vector: /* Set trap vector to exception handler */ la a0, handle_exception csrw CSR_TVEC, a0 @@ -210,7 +210,7 @@ ENTRY(_start_kernel) * not implement PMPs, so we set up a quick trap handler to just skip * touching the PMPs on any trap. */ - la a0, pmp_done + la a0, .Lpmp_done csrw CSR_TVEC, a0 li a0, -1 @@ -218,7 +218,7 @@ ENTRY(_start_kernel) li a0, (PMP_A_NAPOT | PMP_R | PMP_W | PMP_X) csrw CSR_PMPCFG0, a0 .align 2 -pmp_done: +.Lpmp_done: /* * The hartid in a0 is expected later on, and we have no firmware @@ -282,12 +282,12 @@ pmp_done: /* Clear BSS for flat non-ELF images */ la a3, __bss_start la a4, __bss_stop - ble a4, a3, clear_bss_done -clear_bss: + ble a4, a3, .Lclear_bss_done +.Lclear_bss: REG_S zero, (a3) add a3, a3, RISCV_SZPTR - blt a3, a4, clear_bss -clear_bss_done: + blt a3, a4, .Lclear_bss +.Lclear_bss_done: #endif la a2, boot_cpu_hartid XIP_FIXUP_OFFSET a2 @@ -311,7 +311,7 @@ clear_bss_done: call relocate_enable_mmu #endif /* CONFIG_MMU */ - call setup_trap_vector + call .Lsetup_trap_vector /* Restore C environment */ la tp, init_task la sp, init_thread_union + THREAD_SIZE diff --git a/arch/riscv/kernel/mcount.S b/arch/riscv/kernel/mcount.S index 8818a8fa9ff3..ab4dd0594fe7 100644 --- a/arch/riscv/kernel/mcount.S +++ b/arch/riscv/kernel/mcount.S @@ -85,16 +85,16 @@ ENTRY(MCOUNT_NAME) #ifdef CONFIG_FUNCTION_GRAPH_TRACER la t0, ftrace_graph_return REG_L t1, 0(t0) - bne t1, t4, do_ftrace_graph_caller + bne t1, t4, .Ldo_ftrace_graph_caller la t3, ftrace_graph_entry REG_L t2, 0(t3) la t6, ftrace_graph_entry_stub - bne t2, t6, do_ftrace_graph_caller + bne t2, t6, .Ldo_ftrace_graph_caller #endif la t3, ftrace_trace_function REG_L t5, 0(t3) - bne t5, t4, do_trace + bne t5, t4, .Ldo_trace ret #ifdef CONFIG_FUNCTION_GRAPH_TRACER @@ -102,7 +102,7 @@ ENTRY(MCOUNT_NAME) * A pseudo representation for the function graph tracer: * prepare_to_return(&ra_to_caller_of_caller, ra_to_caller) */ -do_ftrace_graph_caller: +.Ldo_ftrace_graph_caller: addi a0, s0, -SZREG mv a1, ra #ifdef HAVE_FUNCTION_GRAPH_FP_TEST @@ -118,7 +118,7 @@ do_ftrace_graph_caller: * A pseudo representation for the function tracer: * (*ftrace_trace_function)(ra_to_caller, ra_to_caller_of_caller) */ -do_trace: +.Ldo_trace: REG_L a1, -SZREG(s0) mv a0, ra diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index 838ff2022fe3..1930b388c3a0 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -26,8 +26,8 @@ SYM_FUNC_START_WEAK(memmove) */ /* Return if nothing to do */ - beq a0, a1, return_from_memmove - beqz a2, return_from_memmove + beq a0, a1, .Lreturn_from_memmove + beqz a2, .Lreturn_from_memmove /* * Register Uses @@ -60,7 +60,7 @@ SYM_FUNC_START_WEAK(memmove) * small enough not to bother. */ andi t0, a2, -(2 * SZREG) - beqz t0, byte_copy + beqz t0, .Lbyte_copy /* * Now solve for t5 and t6. @@ -87,14 +87,14 @@ SYM_FUNC_START_WEAK(memmove) */ xor t0, a0, a1 andi t1, t0, (SZREG - 1) - beqz t1, coaligned_copy + beqz t1, .Lcoaligned_copy /* Fall through to misaligned fixup copy */ -misaligned_fixup_copy: - bltu a1, a0, misaligned_fixup_copy_reverse +.Lmisaligned_fixup_copy: + bltu a1, a0, .Lmisaligned_fixup_copy_reverse -misaligned_fixup_copy_forward: - jal t0, byte_copy_until_aligned_forward +.Lmisaligned_fixup_copy_forward: + jal t0, .Lbyte_copy_until_aligned_forward andi a5, a1, (SZREG - 1) /* Find the alignment offset of src (a1) */ slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ @@ -153,10 +153,10 @@ misaligned_fixup_copy_forward: mv t3, t6 /* Fix the dest pointer in case the loop was broken */ add a1, t3, a5 /* Restore the src pointer */ - j byte_copy_forward /* Copy any remaining bytes */ + j .Lbyte_copy_forward /* Copy any remaining bytes */ -misaligned_fixup_copy_reverse: - jal t0, byte_copy_until_aligned_reverse +.Lmisaligned_fixup_copy_reverse: + jal t0, .Lbyte_copy_until_aligned_reverse andi a5, a4, (SZREG - 1) /* Find the alignment offset of src (a4) */ slli a6, a5, 3 /* Multiply by 8 to convert that to bits to shift */ @@ -215,18 +215,18 @@ misaligned_fixup_copy_reverse: mv t4, t5 /* Fix the dest pointer in case the loop was broken */ add a4, t4, a5 /* Restore the src pointer */ - j byte_copy_reverse /* Copy any remaining bytes */ + j .Lbyte_copy_reverse /* Copy any remaining bytes */ /* * Simple copy loops for SZREG co-aligned memory locations. * These also make calls to do byte copies for any unaligned * data at their terminations. */ -coaligned_copy: - bltu a1, a0, coaligned_copy_reverse +.Lcoaligned_copy: + bltu a1, a0, .Lcoaligned_copy_reverse -coaligned_copy_forward: - jal t0, byte_copy_until_aligned_forward +.Lcoaligned_copy_forward: + jal t0, .Lbyte_copy_until_aligned_forward 1: REG_L t1, ( 0 * SZREG)(a1) @@ -235,10 +235,10 @@ coaligned_copy_forward: REG_S t1, (-1 * SZREG)(t3) bne t3, t6, 1b - j byte_copy_forward /* Copy any remaining bytes */ + j .Lbyte_copy_forward /* Copy any remaining bytes */ -coaligned_copy_reverse: - jal t0, byte_copy_until_aligned_reverse +.Lcoaligned_copy_reverse: + jal t0, .Lbyte_copy_until_aligned_reverse 1: REG_L t1, (-1 * SZREG)(a4) @@ -247,7 +247,7 @@ coaligned_copy_reverse: REG_S t1, ( 0 * SZREG)(t4) bne t4, t5, 1b - j byte_copy_reverse /* Copy any remaining bytes */ + j .Lbyte_copy_reverse /* Copy any remaining bytes */ /* * These are basically sub-functions within the function. They @@ -258,7 +258,7 @@ coaligned_copy_reverse: * up from where they were left and we avoid code duplication * without any overhead except the call in and return jumps. */ -byte_copy_until_aligned_forward: +.Lbyte_copy_until_aligned_forward: beq t3, t5, 2f 1: lb t1, 0(a1) @@ -269,7 +269,7 @@ byte_copy_until_aligned_forward: 2: jalr zero, 0x0(t0) /* Return to multibyte copy loop */ -byte_copy_until_aligned_reverse: +.Lbyte_copy_until_aligned_reverse: beq t4, t6, 2f 1: lb t1, -1(a4) @@ -285,10 +285,10 @@ byte_copy_until_aligned_reverse: * These will byte copy until they reach the end of data to copy. * At that point, they will call to return from memmove. */ -byte_copy: - bltu a1, a0, byte_copy_reverse +.Lbyte_copy: + bltu a1, a0, .Lbyte_copy_reverse -byte_copy_forward: +.Lbyte_copy_forward: beq t3, t4, 2f 1: lb t1, 0(a1) @@ -299,7 +299,7 @@ byte_copy_forward: 2: ret -byte_copy_reverse: +.Lbyte_copy_reverse: beq t4, t3, 2f 1: lb t1, -1(a4) @@ -309,7 +309,7 @@ byte_copy_reverse: bne t4, t3, 1b 2: -return_from_memmove: +.Lreturn_from_memmove: ret SYM_FUNC_END(memmove) -- 2.42.0