From: kernel test robot <lkp@intel.com>
To: Otavio Salvador <otavio@ossystems.com.br>
Cc: oe-kbuild-all@lists.linux.dev
Subject: [freescale-fslc:5.15-2.2.x-imx 3984/25021] drivers/phy/phy-mixel-lvds-combo.c:34: warning: "SS" redefined
Date: Sat, 7 Oct 2023 23:44:52 +0800 [thread overview]
Message-ID: <202310072347.LC7022Ob-lkp@intel.com> (raw)
Hi Liu,
FYI, the error/warning still remains.
tree: https://github.com/Freescale/linux-fslc 5.15-2.2.x-imx
head: 3a95b5654979d1c2d61616bf60249ed3a98dcfbc
commit: 27e9b835ef416f1f11f2944be449bda6577585a7 [3984/25021] phy: Add Mixel LVDS combo PHY support
config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20231007/202310072347.LC7022Ob-lkp@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231007/202310072347.LC7022Ob-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202310072347.LC7022Ob-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/phy/phy-mixel-lvds-combo.c:34: warning: "SS" redefined
34 | #define SS 0x20
|
In file included from arch/x86/include/uapi/asm/ptrace.h:6,
from arch/x86/include/asm/ptrace.h:7,
from arch/x86/include/asm/math_emu.h:5,
from arch/x86/include/asm/processor.h:13,
from arch/x86/include/asm/cpufeature.h:5,
from arch/x86/include/asm/thread_info.h:53,
from include/linux/thread_info.h:60,
from arch/x86/include/asm/preempt.h:7,
from include/linux/preempt.h:78,
from include/linux/smp.h:110,
from include/linux/lockdep.h:14,
from include/linux/mutex.h:17,
from include/linux/notifier.h:14,
from include/linux/clk.h:14,
from drivers/phy/phy-mixel-lvds-combo.c:15:
arch/x86/include/uapi/asm/ptrace-abi.h:23: note: this is the location of the previous definition
23 | #define SS 16
|
vim +/SS +34 drivers/phy/phy-mixel-lvds-combo.c
33
> 34 #define SS 0x20
35 #define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
36 #define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
37 #define CH_PHSYNC(id) BIT(0 + ((id) * 2))
38 #define CH_PVSYNC(id) BIT(1 + ((id) * 2))
39
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
reply other threads:[~2023-10-07 15:45 UTC|newest]
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