From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com,
matthew.d.roper@intel.com, jonathan.cavitt@intel.com,
saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com,
nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH v11 4/7] drm/i915: No TLB invalidation on suspended GT
Date: Tue, 10 Oct 2023 17:02:45 -0700 [thread overview]
Message-ID: <20231011000248.2181018-5-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231011000248.2181018-1-jonathan.cavitt@intel.com>
In case of GT is suspended, don't allow submission of new TLB invalidation
request and cancel all pending requests. The TLB entries will be
invalidated either during GuC reload or on system resume.
Signed-off-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: John Harrison <john.c.harrison@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 1 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 21 +++++++++++++------
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 7 +++++++
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 6af65d44b1a02..9a743d7059628 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -536,4 +536,5 @@ int intel_guc_invalidate_tlb_engines(struct intel_guc *guc);
int intel_guc_invalidate_tlb_guc(struct intel_guc *guc);
int intel_guc_tlb_invalidation_done(struct intel_guc *guc,
const u32 *payload, u32 len);
+void wake_up_all_tlb_invalidate(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8e5a79ecfc2a2..9d5f8cccaa592 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1796,13 +1796,25 @@ static void __guc_reset_context(struct intel_context *ce, intel_engine_mask_t st
intel_context_put(parent);
}
-void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)
+void wake_up_all_tlb_invalidate(struct intel_guc *guc)
{
struct intel_guc_tlb_wait *wait;
+ unsigned long i;
+
+ if (!HAS_GUC_TLB_INVALIDATION(guc_to_gt(guc)->i915))
+ return;
+
+ xa_lock_irq(&guc->tlb_lookup);
+ xa_for_each(&guc->tlb_lookup, i, wait)
+ wake_up(&wait->wq);
+ xa_unlock_irq(&guc->tlb_lookup);
+}
+
+void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled)
+{
struct intel_context *ce;
unsigned long index;
unsigned long flags;
- unsigned long i;
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
@@ -1833,10 +1845,7 @@ void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stall
* The full GT reset will have cleared the TLB caches and flushed the
* G2H message queue; we can release all the blocked waiters.
*/
- xa_lock_irq(&guc->tlb_lookup);
- xa_for_each(&guc->tlb_lookup, i, wait)
- wake_up(&wait->wq);
- xa_unlock_irq(&guc->tlb_lookup);
+ wake_up_all_tlb_invalidate(guc);
}
static void guc_cancel_context_requests(struct intel_context *ce)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 98b103375b7ab..750cb63503dd7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -688,6 +688,8 @@ void intel_uc_suspend(struct intel_uc *uc)
/* flush the GSC worker */
intel_gsc_uc_flush_work(&uc->gsc);
+ wake_up_all_tlb_invalidate(guc);
+
if (!intel_guc_is_ready(guc)) {
guc->interrupts.enabled = false;
return;
@@ -736,6 +738,11 @@ static int __uc_resume(struct intel_uc *uc, bool enable_communication)
intel_gsc_uc_resume(&uc->gsc);
+ if (HAS_GUC_TLB_INVALIDATION(gt->i915)) {
+ intel_guc_invalidate_tlb_engines(guc);
+ intel_guc_invalidate_tlb_guc(guc);
+ }
+
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2023-10-11 0:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 0:02 [Intel-gfx] [PATCH v11 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 1/7] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt
2023-10-11 9:00 ` Nirmoy Das
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 2/7] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-11 9:00 ` Nirmoy Das
2023-10-11 17:44 ` John Harrison
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-11 9:01 ` Nirmoy Das
2023-10-11 17:52 ` John Harrison
2023-10-11 0:02 ` Jonathan Cavitt [this message]
2023-10-11 11:09 ` [Intel-gfx] [PATCH v11 4/7] drm/i915: No TLB invalidation on suspended GT Nirmoy Das
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 5/7] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-11 9:03 ` Nirmoy Das
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-11 9:04 ` Nirmoy Das
2023-10-11 0:02 ` [Intel-gfx] [PATCH v11 7/7] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-11 9:05 ` Nirmoy Das
2023-10-11 4:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-11 4:17 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-11 4:30 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-11 8:24 ` [Intel-gfx] [PATCH v11 0/7] " Tvrtko Ursulin
2023-10-11 18:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
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